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Analog Designer
Designs and tests high-speed analog and mixed-signal circuits (GDDR, PLLs, SerDes) for next-gen AMD processors using Verilog, C++, and Cadence tools.
Sr. Silicon Design Engineer
Design and verify next-gen GPU/CPU/SoC silicon, writing RTL in Verilog/SystemVerilog/VHDL and using ASIC tools to optimize power, timing, and area for AMD processors.
MTS Silicon Design Engineer
Design and verify ASICs and SoCs for next-gen processors using Verilog, VHDL, and UVM testbenches in a distributed compute environment.
Sr. Silicon Design Engineer
Design and verify next-gen ASICs and SoCs for AMD/Xilinx chips using RTL, Verilog/SystemVerilog/VHDL, and C/C++/Python in Linux environments.
Sr. Silicon Design Engineer
Design and verify next-gen ASIC/SOC components for AMD’s processors using Verilog/VHDL, SystemVerilog, UVM, and PCIe/AXI protocols.
MTS Silicon Design Engineer
Design and verify next-gen CPU/GPU/SoC silicon, writing Verilog/SystemVerilog tests and collaborating with RTL teams to debug pre-silicon issues.
Sr. Software Development Engineer
Design and develop low-level software like OS kernels, compilers, and EDA tools for next-gen CPUs and AI accelerators, optimizing CPU efficiency and hardware-software interaction.
MTS Silicon Design Engineer
Design and verify ASICs/FPGAs for high-performance computing using SystemVerilog, UVM, and industry tools like Synopsys VCS and Cadence IES.
Sr. Silicon Design Engineer
Design and verify next-gen semiconductor components for AMD’s processors, focusing on ASIC, GPU, and SOC architecture using Verilog/VHDL, RTL, and EDA tools.
PMTS Software Development Engineer
Develop and optimize low-level GPU kernels to accelerate ML model training and inference, using parallel computing and quantization techniques while collaborating with researchers and engineers.
PMTS Silicon Design Engineer
Designs and codes processor-core RTL, collaborates on microarchitecture, and drives synthesis, timing, and power optimization for next-gen CPUs at AMD.
MTS Silicon Design Engineer
Designs and verifies next-gen CPU hardware using C++, Verilog, and UVM; runs simulations and formal checks to catch bugs before silicon tape-out.
Sr. Silicon Design Engineer
Design and verify next-gen CPU/GPU silicon, writing RTL in SystemVerilog, running UVM tests, and optimizing power/timing for AMD processors.
Sr. Silicon Design Engineer
Design and verify next-gen semiconductor chips using C/C++/Python and HDLs like Verilog/SystemVerilog; drive ASIC flows from RTL to synthesis, place-and-route, timing, and power analysis.
MTS Silicon Design Engineer
Design and verify silicon for AMD Instinct AI accelerators, collaborating with architects and engineers to debug RTL, firmware, and test failures using Verilog, SystemVerilog, and C/C++ in a distributed compute environment.
MTS Silicon Design Engineer
Design and verify next-gen semiconductor chips using Verilog/VHDL, UVM, and SystemVerilog test benches in a Linux environment.
Sr. Silicon Design Engineer
Designs and verifies next-gen processor IP using SystemVerilog, C/C++, Python, and EDA tools to ensure functional correctness and performance in Linux environments.
Systems Design Engineer
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And…
Sr. Silicon Design Engineer
Design and verify next-gen processor IP blocks using Verilog/VHDL, C++, and Python; debug RTL, timing, and coverage issues; collaborate with SoC and verification teams.