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Senior Electrical Engineer - FPGA Verification
Senior Electrical Engineer verifies FPGA-based radar designs using SystemVerilog/UVM testbenches and industry simulators, ensuring functional correctness and coverage.
Principal Electrical Engineer - FPGA Verification
Principal Electrical Engineer verifies FPGA-based radar designs using SystemVerilog, UVM, and industry simulators, ensuring functional correctness and coverage for control/signal-processing applications.
FPGA Engineer II
Design and verify FPGA logic in VHDL for multi-gigabit interfaces, RF/EO DSP, and embedded processing using AMD, Altera, and Microchip toolchains.
Principal Electrical Engineer - Digital Circuit Card Design
Principal Electrical Engineer designing high-speed digital circuit boards for military radar systems using CAD tools, signal integrity analysis, and embedded processors.
Senior Electrical Engineer - FPGA Verification
Senior Electrical Engineer verifying FPGA-based radar designs using SystemVerilog, UVM, and industry simulators to ensure functional correctness and coverage.
Hardware Engineer, FPGA
Design and verify digital logic for novel AI hardware using SystemVerilog, collaborating across RTL, verification, and physical design to tape out custom ASICs.
SOC Micro-Architect and RTL Designer
Designs and implements silicon micro-architecture and RTL for high-performance GenAI compute chips, owning subsystems from spec to tapeout and collaborating with verification and physical design teams.
Senior FPGA Prototyping Engineer
Senior FPGA engineer building hardware prototypes and validating next-gen satellite communications ASICs, from FPGA bring-up to first-silicon debug.
Circuit Design Writer - Engineering FRQ
Designs and writes advanced circuit-engineering free-response questions to stress-test AI models, requiring a PhD in EE and 5+ years of shipped analog/digital/power/RF designs.
Principal Silicon Design Verification Engineer
Principal engineer designing and verifying custom silicon chips for Microsoft's cloud infrastructure, using C/C++, SystemVerilog, UVM, and Python to ensure hardware quality and performance.
Principal Design Verification Engineer- SerDes/PHY
Principal Design Verification Engineer builds and runs UVM testbenches to verify multi-Gbps SerDes/PHY IP for AI connectivity, ensuring first-pass silicon success for standards like PCIe Gen 6/7, UALink, and Ethernet.
ASIC Design Verification Engineer
Build and debug SystemVerilog/UVM testbenches for ASIC IP blocks powering 5G networks, from block-level to top-level verification and SW-driven validation.
ASIC Design Verification Engineer
Design and implement SystemVerilog/UVM testbenches to verify ASIC blocks and SoCs powering 5G networks, debug RTL, and ensure silicon reliability before deployment.
Hardware Engineer
Design and optimize FPGA-based hardware for ultra-low-latency trading infrastructure, integrating Ethernet stacks and custom logic to parse and route exchange data efficiently.
Senior AI/ML Engineer
Build and deploy AI agents that automate silicon IP design workflows using RAG, structured tool execution, and EDA tool integration to accelerate spec-to-netlist cycles.
