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Principal Electrical Engineer - FPGA Verification
Principal Electrical Engineer verifies FPGA-based radar designs using SystemVerilog, UVM, and industry simulators, ensuring functional correctness and coverage for control/signal-processing applications.
Senior Electrical Engineer - FPGA Verification
Senior Electrical Engineer verifying FPGA-based radar designs using SystemVerilog, UVM, and industry simulators to ensure functional correctness and coverage.
Senior Software Engineer
Build and certify real-time embedded C software for aerospace electric power systems, following DO-178C and collaborating across the full SDLC.
SoC DFT Technical Manager, Google Cloud
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML…
ASIC Design Verification Engineer
Build and debug SystemVerilog/UVM testbenches for ASIC IP blocks powering 5G networks, from block-level to top-level verification and SW-driven validation.
ASIC Design Verification Engineer
Design and implement SystemVerilog/UVM testbenches to verify ASIC blocks and SoCs powering 5G networks, debug RTL, and ensure silicon reliability before deployment.
BE CAD Physical Impl and AI Engineer
Build and evolve Ericsson’s FlowJam CAD framework for ASIC physical implementation, integrating AI-driven optimization and partnering with Physical Design teams to improve power, performance, and productivity.
Senior Silicon Physical Design Engineer, Google Cloud
Designs and optimizes custom silicon for Google Cloud, focusing on performance, power, and area while collaborating with cross-functional hardware teams.
Software Developer in Test
Build and maintain automated tests (UI, API, integration) for a data-security product line, integrating them into CI/CD pipelines and ensuring robust verification of encryption and identity-management features.
Senior FPGA Design Engineer / Hardware Engineer
Designs and optimizes FPGA-based hardware systems to reduce latency and increase throughput for proprietary trading strategies, using SystemVerilog and automated verification.
[AI반도체] SoC Design Engineer
Designs and verifies RTL for AI NPUs, focusing on SoC blocks like interfaces, power management, and clocking using Verilog/SystemVerilog and scripting (Python/Tcl).
Manager / Senior Manager, Design Verification
Lead a team to verify low-power wireless SoC designs using SystemVerilog/UVM, ensuring robust IP and SoC delivery across global projects.
Lead Engineer, IC Design
Lead a team to implement and sign off on timing constraints, synthesis, and static timing analysis for high-performance SoCs and ASICs using Cadence or Synopsys EDA tools.
Staff Engineer, IC Design
Design and implement low-power digital IP blocks (Verilog/SystemVerilog) for SoCs, driving RTL from spec to tape-out while meeting PPA targets and collaborating with verification and SoC teams.
Senior Software Developer
Design and build call-processing software and management systems for Windows using C#, .NET, C++, and VoIP/SIP protocols, following Agile practices.
Senior FPGA Engineer (TS/SCI)
Design and verify mission-critical FPGA firmware for high-power satellites, implementing real-time control, networking, and RF systems in VHDL/SystemVerilog.
Sr Principal Engineer Design, CPU Microarchitecture & RTL Design
Lead the microarchitecture and RTL design of next-gen AI-enabled RISC-V CPU cores, including vector/matrix processing engines, while balancing performance, power, and area constraints.