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Embedded Firmware Engineer
Develop and debug FPGA firmware and embedded software for handheld medical ultrasound devices, integrating MCU/MPU subsystems and ensuring compliance with medical standards.
AI/ML Camera Lead Engineer
Lead the design of camera and image-processing ASIC IP blocks using RTL, synthesis, and PPA analysis, while driving GenAI tools for hardware workflows and agentic AI solutions.
CPU Micro-architect/RTL Designer
Designs and implements CPU micro-architectures and RTL for high-performance, low-power chips, collaborating with architects and verification teams.
Power Management IC Design
Designs and verifies mixed-signal power-management ICs for compute, data center, automotive, and industrial systems using Cadence, Spectre, MATLAB, and Verilog/AMS.
Senior ASIC Implementation Engineer, Low Power AI
Senior ASIC Implementation Engineer, Low Power AI Location: Markham, Ontario, Canada Department: ASICS Engineering Work Location: onsite Company: Qualcomm Canada ULC Job Area: Engineering Group, Engineering Group >…
SOC Architect
Designs and optimizes System-on-Chip (SoC) architectures for mobile/IoT/XR platforms, focusing on performance, power, and security trade-offs.
Physical Design Engineer, Mixed Signal IP
Designs and implements mixed-signal IP blocks (DDR, USB, PCI, PLL) using nanometer technologies, focusing on physical design flow, timing closure, and verification to tape out high-quality silicon.
CPU RTL Design Engineer
Design and implement CPU microarchitecture and RTL for high-performance, low-power devices, collaborating with architects and verification teams.
IC Design Engineer
Designs and verifies analog and mixed-signal ICs to emulate obsolete microcircuits for defense systems, using tools like Verilog/VHDL and Python.
Embedded Linux Software Engineer
Develop embedded Linux and firmware for water-pipeline monitoring systems using C++ on STM32, Python on Linux SoCs, and FPGA IP cores (VHDL).
Software Engineer
Develop embedded C/C++ firmware and FPGA-based (Verilog) designs for microprocessor-based power-grid controls, optimizing for low-power and high-throughput data.
Campus FPGA Engineer (Intern)
Designs ultra-low-latency FPGA-based systems for real-time trading acceleration using RTL and hardware design, working alongside experts in a research-driven finance firm.
FPGA Engineer
Designs and implements FPGA-based hardware solutions for embedded systems, focusing on signal processing and real-time applications.
Product Development Architect
Lead a team to implement and tape out high-performance ASIC/APU/dGPU designs for AI, gaming consoles, and automotive using RTL-to-GDS flows, PnR, timing closure, and physical verification.
Embedded Software Engineer, Physical AI
Develop embedded C/C++ software and Linux platform support for AMD Adaptive SoCs and Ryzen AI Embedded processors, building computer vision, graphics, and edge AI pipelines for robotics and industrial automation.
Senior Staff Software Development Engineer
Senior engineer designing and implementing embedded firmware for AMD’s next-gen networking products, collaborating with silicon, driver, and test teams to deliver high-performance network stacks for cloud and AI systems.
Digital Design Designer
Designs digital IP blocks and SoCs for automotive systems, writing RTL in Verilog/VHDL and collaborating with verification, physical implementation, and validation teams.
Interconnect Design Engineer
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive…
Lead Firmware Engineer
Lead a global team to design, develop, and deploy embedded firmware for UPS systems using C/C++, RTOS, and control systems, ensuring product quality and alignment with customer needs.
Staff Electrical and Electronic Design Engineer
Staff Electrical and Electronic Design Engineer - Future Forward Location: Sunnyvale, CA, us Company Description It started with a simple idea: what if surgery could be less invasive and recovery less painful? Nearly…