Tech jobs

ASIC Design Verification Engineer

HybridNorth America

backbone embedded-software ethernet git linux +6 skills

Design and implement SystemVerilog/UVM testbenches to verify ASIC blocks and SoCs powering 5G networks, debug RTL, and ensure silicon reliability before deployment.

Tower Research Capital

Hardware Engineer

HybridAPAC

bash cpp ethernet fpga linux +8 skills

Design and optimize FPGA-based hardware for ultra-low-latency trading infrastructure, integrating Ethernet stacks and custom logic to parse and route exchange data efficiently.

Advanced Micro Devices, Inc

agentic-ai ai api autogen automation +13 skills

Senior AI/ML Engineer

EuropeSenior

Serbia

Build and deploy AI agents that automate silicon IP design workflows using RAG, structured tool execution, and EDA tool integration to accelerate spec-to-netlist cycles.

The Aerospace Corporation

On-siteNorth AmericaFull-timeSenior

Senior Hardware Security Engineer

bash containerization cpp data-science embedded-software +13 skills

Design and verify secure FPGA/ASIC designs, assess hardware security risks, and develop mitigations for space systems used by defense and intelligence agencies.

166 400 – 249 600 $

Maven

Senior FPGA Design Engineer / Hardware Engineer

Open 63d UKSenior

fpga maven python systemverilog tcl

Designs and optimizes FPGA-based hardware systems to reduce latency and increase throughput for proprietary trading strategies, using SystemVerilog and automated verification.

Astera Labs

ai ethernet pcie systemverilog verilog

Tech Lead Design Engineer Location: San Jose, California, United States Department: Board Validation Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By…

모빌린트

ai cpp fpga java perl +4 skills

[AI반도체] SoC Design Engineer

APAC

South Korea

Designs and verifies RTL for AI NPUs, focusing on SoC blocks like interfaces, power management, and clocking using Verilog/SystemVerilog and scripting (Python/Tcl).

Cambridge Consultants

Open 56d UK Licensed UK sponsor H-1B sponsor history

Contractors - FPGA Engineers

fpga systemverilog verilog vhdl

Contract FPGA engineers to design and implement Verilog/VHDL for satellite telecoms projects using Xilinx ISE and SystemVerilog.

Cambridge Consultants

Open 56d UK Licensed UK sponsor H-1B sponsor history

Electronics / Software Engineer

ai cpp embedded-software embedded-systems rust +3 skills

Design and implement embedded systems, hardware, and software for client projects across industries like robotics, consumer devices, and defense, using C, SystemVerilog, PCB design, and more.

Cambridge Consultants

Open 56d UK Licensed UK sponsor H-1B sponsor history

Graduate Electronics & Software Engineer (2026 start)

ai cpp embedded-software embedded-systems rust +3 skills

Graduate electronics and software engineer designing embedded systems, hardware, and firmware for diverse client projects like robotics, LEGO products, and defense systems.

Cadence Design Systems

automation cad cpp python signal-processing +1 skills

Firmware Design Engineer

North AmericaFull-time

Canada

Design and implement firmware for high-speed SERDES PHY IP, collaborating on architecture, verification, post-silicon validation, and customer deployment using C/C++ and Python.

73 500 – 136 500 CAD

HybridNorth AmericaInternshipIntern

Digital Design Engineer

embedded-systems systemverilog verilog

Designs and verifies digital logic blocks for low-power wireless microcontroller SoCs using Verilog/SystemVerilog and collaborates with analog and firmware teams.

78 750 – 146 250 $

Manager / Senior Manager, Design Verification

APACFull-timeSenior

ai analytics automation data-analytics fpga +8 skills

Lead a team to verify low-power wireless SoC designs using SystemVerilog/UVM, ensuring robust IP and SoC delivery across global projects.

Staff Engineer, IC Design

APACFull-timeStaff

ai perl python systemverilog tcl +2 skills

Design and implement low-power digital IP blocks (Verilog/SystemVerilog) for SoCs, driving RTL from spec to tape-out while meeting PPA targets and collaborating with verification and SoC teams.

Design Verification Engineer, Low Power UPF/CPF

APACFull-time

ai nlp perl python systemverilog

Lead verification of low-power SoC features using UPF/CPF, building SystemVerilog/UVM testbenches and power-aware test plans to ensure robust, energy-efficient silicon.

PsiQuantum

Open 63d North AmericaFull-timeSenior H-1B sponsor history

Senior Analog / Mixed-Signal IC Design Engineer

ai cadence-virtuoso fiber systemverilog verilog

Designs analog and mixed-signal integrated circuits for quantum computing systems, focusing on data converters, amplifiers, and references using CMOS/SiGe processes and tools like Spectre and Cadence Virtuoso.

180 000 – 197 000 $

PsiQuantum

Open 63d North AmericaFull-timeSenior H-1B sponsor history

Senior Digital System Designer

ai fiber python systemverilog vhdl

Designs and implements low-latency digital systems for a silicon photonics-based quantum computer, using FPGAs, SystemVerilog, and Python.

175 000 – 195 000 $

PsiQuantum

Open 63d North AmericaFull-timeStaff H-1B sponsor history

Staff Digital Design Engineer

ai fiber fpga systemverilog verilog

Designs, implements, and validates FPGA-based digital microarchitectures using Verilog/SystemVerilog for quantum computing systems in Palo Alto.

210 000 – 235 000 $

K2 Space

North AmericaFull-timeSenior

Senior FPGA Engineer (TS/SCI)