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Software Engineer, GenAI Silicon Automation, DeepMind
Build AI-driven infrastructure to automate silicon design workflows, using MLIR/CIRCT and agentic systems to bridge ML models with hardware accelerators.
RTL Design Engineer, Silicon
Designs and codes RTL for custom silicon subsystems using Verilog/VHDL, integrates IP, and runs simulations and checks to deliver high-performance hardware for Google’s products.
Senior SoC and IP Design Engineer, Google Cloud
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…
Staff Engineer, VLSI Design Engineering (SOC Verification, UVM) with 8 to 12 years of experience
Lead verification of complex SoC designs using UVM, SystemVerilog, and formal tools; develop test plans, coverage-driven environments, and automation to validate NAND flash memory subsystems.
Experienced Engineer - FPGA CAD
Build and maintain FPGA CAD tools and automation flows in Python/Tcl to speed up synthesis, place & route, and verification for Ericsson’s radio/RAN compute products.
Hardware Developer / Инженер-схемотехник
Designs and prototypes smart cameras and embedded systems, including schematics, PCB layout, prototyping, debugging, and firmware for STM32/ESP32/AVR microcontrollers.
Senior Engineer - FPGA Design
Designs and optimizes FPGA-based solutions for radio and RAN compute systems, integrating hardware/software components using HDL and industry tools like Vivado or Quartus.
Managing Staff, Embedded Software Engineer - Advanced Energy
Lead a team developing embedded software in C++/C/Verilog/Python for electrosurgical devices, focusing on real-time energy data processing and control systems for minimally invasive surgical robots.
Director, Embedded Memory
Lead a team to design and deliver embedded memory compilers (SRAM, ROM, register files, DPRAM) for SoC integration, setting PPA targets, customer requirements, and silicon validation.
SC Cleated FPGA Engineer
Designs and implements FPGA firmware for AMD/Xilinx Zynq UltraScale MPSoC using Vivado, HDLs, and embedded Linux tooling (Yocto/PetaLinux) in a Central London office.
Avionics FPGA Engineer
Design and verify FPGA-based avionics for autonomous space systems using SystemVerilog/Verilog, debug hardware in the lab, and collaborate on flight-ready systems.
Digital Design Engineer
Designs and debugs RTL for AMD’s Infinity Data Fabric, optimizing for power, timing, and area while collaborating with global teams.
[EMN] Senior IP Design Verification Engineer
Own and execute pre-silicon verification for Silicon IP (e.g., UCIe Interoperability) using UVM/OVM, SystemVerilog, and AXI VIP; debug failures and guide junior engineers.
RTL Design Engineer – FPGA High-Speed Connectivity IP
Design and validate high-performance RTL IPs for FPGA high-speed connectivity subsystems using VHDL/Verilog and AMD/Xilinx toolchains.
Software Engineer, AI Model Training - Team Lead
Leads a team of developers to build and maintain AI training datasets, ensuring quality and efficiency while mentoring staff and reporting progress to clients.
PLL Design Engineer
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And…
Formal Verification Architect
Architect and lead formal verification strategies for complex ASIC designs, guiding teams to ensure silicon quality for next-gen processors and I/O technologies.
Staff Silicon Design Engineer
Designs and executes SoC verification for AMD’s next-gen ASIC and FPGA chips, writing testbenches in SystemVerilog/UVM and debugging failures to ensure bug-free silicon.
Senior AI/ML Engineer
Build and deploy AI agents that automate silicon IP design using RAG, agentic workflows, and EDA tool integration to accelerate spec-to-netlist pipelines.
Silicon Design Engineer
Lead verification of AMD’s IOHUB subsystem, defining test plans and collaborating with global teams to ensure high-performance interconnect IP meets design specs.