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Senior Hardware Security Engineer
Designs and secures hardware systems for space missions, focusing on satellite, launch, and ground systems to protect against cyber threats.
FPGA Engineer I
Design and verify FPGA logic in VHDL for defense systems, using tools like Xilinx Vivado and Altera Quartus, and support lab integration and documentation.
Senior Subsystem Design Verification Engineer
Design and verify complex silicon subsystems for Arm-based platforms using SystemVerilog/UVM, ensuring functionality, performance, and coverage closure.
Junior Digital Design/DfT Engineer
Designs and verifies digital circuits for IoT and automotive chips using VHDL/Verilog, SystemVerilog, and Python, with a focus on signal processing and embedded software integration.
Lead Design Verification Engineer
Lead pre-silicon verification of semiconductor IPs and SoCs using UVM, SystemVerilog, and industry simulators to ensure functional correctness before tape-out.
FPGA Silicon Design Verification Engineer
Designs and runs SystemVerilog/UVM testbenches to verify FPGA IP blocks and SoC designs, using coverage-driven methods and assertions to ensure first-pass silicon success.
FPGA Silicon Design Verification Engineer
Design Verification Engineer builds UVM testbenches and runs pre-silicon verification for FPGA DFT logic like scan, MBIST, and JTAG to ensure silicon quality before tape-out.
Semi-Conductor Design Verification Engineer
Designs and verifies digital IP blocks and SoC architectures using SystemVerilog/UVM to ensure functional correctness of high-speed ASIC components like Ethernet switches and PCIe controllers.
Software Engineer (Electronic Test Automation)***
Build Python automation tools, dashboards, and AI-assisted workflows for semiconductor test development, then validate and analyze results to improve efficiency.
Senior FPGA Design Engineer
Design and verify FPGA-based systems using VHDL/SystemVerilog for aerospace/defense applications, collaborating with hardware and systems teams to meet DoD requirements.
Senior FPGA Design Engineer
Design and verify FPGA-based systems in VHDL/SystemVerilog for aerospace/defense applications, including RF/EO DSP, data links, and embedded processing.
DFT Digital Design Engineer (f/m/d)
Design-for-Test engineer implementing scan, MBIST, JTAG, and ATPG flows to improve SoC test coverage and silicon yield while collaborating with cross-functional teams.
Director, ASIC Design & Front-End Implementation
Lead a team designing and implementing next-generation networking ASICs, guiding RTL development, implementation, and tapeout while collaborating with cross-functional teams to meet performance and schedule targets.
Hardware Software Integration Engineer
Designs and builds software tooling, firmware, and infrastructure to accelerate semiconductor development cycles, working closely with hardware teams in EDA, verification, or post-silicon environments using C, C++, and Python.
Director, ASIC Design & Front-End Implementation
Lead a team designing and implementing high-performance networking ASICs from architecture to tapeout, collaborating with cross-functional teams to deliver silicon for HPE's networking products.
Senior FPGA Design Engineer
Design and verify FPGA-based systems in VHDL for aerospace/defense applications, including gigabit interfaces, DSP, and embedded processing, while collaborating with systems engineers and leading small teams.
Senior FPGA Design Engineer
Senior FPGA engineer designing and verifying VHDL-based signal-processing and interface logic for aerospace/defense systems using Xilinx, Altera, and Microsemi devices.
Staff Silicon Design Engineer
Design engineer verifies next-gen ASIC and FPGA SoCs using SystemVerilog/UVM, debugging failures and ensuring functional coverage for AMD’s high-performance computing and AI products.
Hardware Engineer Intern
Hardware Engineer Intern contributing to FPGA development and hardware improvements at a global trading firm, using VHDL/Verilog and collaborating with trading and tech teams.
Senior CAD Engineer, RTL Design, Silicon, Google Cloud
Design and verify custom silicon for Google’s TPU AI accelerators, leading CAD methodology and RTL design flows to power next-gen AI/ML systems.