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Silicon Design Verification Staff Engineer
Design verification engineer building PCIe interconnect IP testbenches using UVM/SystemVerilog to validate high-performance ASIC features for AMD’s GPUs, APUs, servers, and consoles.
Staff Design Verification Engineer
Design verification engineer at AMD, building and automating tests for next-gen network processors and SmartNICs using UVM, SystemVerilog, and AI-assisted workflows.
Design Verification Engineer
Design Verification Engineer at AMD builds and runs testbenches in SystemVerilog/UVM to validate DDR5/LPDDR5 memory interfaces and DFI protocols for server products.
Principal Staff Silicon Design Engineer, DDR Verification
Lead verification of DDR5/LPDDR5 memory interfaces for server products using SystemVerilog, UVM, and formal methods; mentor engineers and collaborate with hardware, firmware, and software teams.
Staff Design Verification Engineer
Design Verification Engineer at AMD building and running testbenches for DDR5/LPDDR5 memory interfaces using SystemVerilog, UVM, and C/C++ to validate server memory products.
RTL Design Lead, IP Design
Lead a team designing and integrating RTL for SoC subsystems, ensuring first-pass silicon success through collaboration with architecture, verification, and physical design teams.
Lead Logic Design Engineer
Lead MTS Logic Design Location: Vught, UNAVAILABLE, NL Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead Member of Technical Staff Logic Design…
Design Verification Principal Engineer
Principal Engineer designs and verifies memory controller IP for DDR/HBM/GDDR DRAM, building SystemVerilog testbenches and coverage-driven regression suites.
RTL Design Lead - IP Design
Lead RTL design for IP subsystems, integrating AMD and third-party IPs, ensuring first-pass silicon success through quality checks and collaboration with verification and physical design teams.
Design Verification Engineer, PCIe Controller
Design Verification Engineer for PCIe and CXL controller IP, building testbenches and coverage plans in SystemVerilog/UVM to validate new controller features before tape-out.
Hardware Security Engineer
Design and develop secure hardware IPs like post-quantum crypto accelerators and random number generators using Verilog/SystemVerilog, collaborating with architects and software teams to meet security and quality standards.
Software Development Engineer
Develops automation tools and flows for front-end chip design verification, synthesis, and package generation using SystemVerilog, Python, and EDA tools.
Principal PCIe Logic Design Engineer
Principal PCIe Logic Design Location: Hillsboro, OR, US Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Principal Design engineer to join our…
Logic Design Engineer
PE Logic Design Location: Bangalore, KA, IN Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Principal Design engineer to join our PCIe IP design…
RTL Design Engineer
Designs and validates synthesizable RTL for digital IPs and SoC subsystems using Verilog/SystemVerilog, ensuring clean signoff through Lint, CDC, RDC, and synthesis checks.
Senior IP Design Verification Engineer
Own and execute pre-silicon verification for Silicon IP (e.g., UCIe Interoperability) using UVM/System Verilog, debug failures, and guide junior engineers in ASIC/SoC verification flows.
Senior Analog/Mixed-Signal IC Designer Automotive
Design and lead analog/mixed-signal ICs for automotive electrification and smart power, owning the full flow from spec to silicon and coaching junior engineers.
Senior Analog/Mixed-Signal IC Designer Automotive
Designs and verifies analog/mixed-signal ASICs for automotive electrification and smart-power systems, leading architecture, verification, and product release while coaching junior engineers.
Silicon Validation Engineering Manager, Cloud
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML…
Senior FPGA Prototyping Engineer
Senior FPGA engineer builds FPGA-based prototypes and validation platforms to accelerate ASIC development for next-gen communications and satellite hardware, enabling early software/firmware integration and silicon bring-up.