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Senior Silicon Test Engineer, ATE
Develop and deploy ATE solutions for high-volume IC testing, designing load boards, probe cards, and test programs to validate and optimize SoC performance in Google’s custom silicon workflow.
Avionics FPGA Engineer
Design and verify FPGA-based avionics for autonomous space systems using SystemVerilog/Verilog, debug hardware in the lab, and collaborate on flight-ready systems.
[EMN] Senior IP Design Verification Engineer
Own and execute pre-silicon verification for Silicon IP (e.g., UCIe Interoperability) using UVM/OVM, SystemVerilog, and AXI VIP; debug failures and guide junior engineers.
Hardware Systems Design Engineer, Circuit Board
Senior Electrical Engineer designing and debugging cloud compute server systems and PCB boards, leading architecture, schematics, and production testing.
Silicon Design Engineer
Lead verification of AMD’s IOHUB subsystem, defining test plans and collaborating with global teams to ensure high-performance interconnect IP meets design specs.
Silicon Design Verification Staff Engineer
Design verification engineer building PCIe interconnect IP testbenches using UVM/SystemVerilog to validate high-performance ASIC features for AMD’s GPUs, APUs, servers, and consoles.
Staff Silicon Design Verification Engineer, PCIe
Verify next-gen PCIe controller designs for AMD’s SoCs, using SystemVerilog/UVM testbenches and low-power techniques to ensure performance and power targets for AI, gaming, and server chips.
Lead Logic Design Engineer
Lead MTS Logic Design Location: Vught, UNAVAILABLE, NL Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead Member of Technical Staff Logic Design…
Logic Design Engineer
SMTS Logic Design Location: Montreal, UNAVAILABLE, CA Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Senior Member of…
Design Verification Engineer, PCIe Controller
Design Verification Engineer for PCIe and CXL controller IP, building testbenches and coverage plans in SystemVerilog/UVM to validate new controller features before tape-out.
Principal PCIe Logic Design Engineer
Principal PCIe Logic Design Location: Hillsboro, OR, US Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Principal Design engineer to join our…
Logic Design Engineer
PE Logic Design Location: Bangalore, KA, IN Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Principal Design engineer to join our PCIe IP design…
Embedded Hardware Development Engineer
Designs and validates embedded hardware for automotive systems, focusing on SoC requirements, schematic/layout contributions, and bring-up/validation using Python automation and tools like Lauterbach Trace32.
Senior IP Design Verification Engineer
Own and execute pre-silicon verification for Silicon IP (e.g., UCIe Interoperability) using UVM/System Verilog, debug failures, and guide junior engineers in ASIC/SoC verification flows.
Server BMC Firmware Engineer
Develop and maintain BMC firmware for Rebellion’s AI servers, implementing OpenBMC-based power/thermal control, IPMI/Redfish interfaces, and host-BMC communication.
Embedded Linux Platform Engineer
Develops and maintains embedded Linux platforms for networking products, focusing on Yocto builds, kernel upgrades, device drivers, and hardware-software integration on ARM64 and x86_64.
Principal Security Engineer
Principal Security Engineer designs and implements secure hardware and firmware for Microsoft's cloud infrastructure, focusing on security protocols, hardware accelerators, and trusted computing.
Compute Hardware Technical Leader (Hybrid)
Lead the design and delivery of high-performance compute hardware systems, including x86/ARM-based servers, DDR memory, and PCIe interfaces, for Cisco’s Unified Computing portfolio.
Sr. Hardware Engineering Manager
Lead a team of hardware engineers designing next-gen GPU and AI compute servers, guiding platforms from architecture through high-volume production for Hyperscalers.