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Staff Engineer - IC Design
Designs and implements reusable digital IP blocks (Verilog/SystemVerilog) for low-power wireless SoCs, focusing on PPA targets and AMBA/peripheral IP like SPI, UART, and DMA.
Manager / Senior Manager – Design Verification
Lead a team to verify low-power wireless SoC designs using SystemVerilog/UVM, ensuring robust IP and chip-level functionality across global projects.
Amazon Senior Design Verification Engineer, SSG
Designs and implements verification environments for advanced hardware blocks using SystemVerilog/UVM, driving test plans and low-power checks to ensure silicon-quality devices.
SOC Design Engineer
Designs and verifies System-on-Chip (SoC) subsystems using Verilog/SystemVerilog, integrating high-speed IPs like PCIe and DDR, and collaborating with verification and backend teams.
Ingénieur en conception de micrologiciel - Firmware Design Engineer
Designs and implements firmware for high-speed SERDES PHY IP, collaborating on architecture, verification, post-silicon validation, and customer deployment using C/C++ and Python.
Senior Hardware Security Engineer
Design and verify secure hardware for space systems, assess FPGA/ASIC vulnerabilities, and develop guidance to mitigate threats in embedded and cyber-physical systems.
Emulation Front-End Infrastructure Engineer
Engineer scalable compilation and synthesis flows for NVIDIA’s hardware emulation platforms, using EDA tools like Synopsys and Cadence to validate complex chip designs before fabrication.
PMTS ASIC Digital Design IP ENGINEERING
Designs and implements high-performance processor cores and SoC subsystems using Verilog/SystemVerilog, driving microarchitecture, RTL coding, and PPA optimization from concept to silicon bring-up.
Sr Mgr/Dep Director ASIC Digital Design IP ENGINEERING
Leads a team to design and tape out next-gen processor and SoC IP, guiding RTL development, verification, and PPA optimization for high-performance, low-power ASICs.
Amazon Chip Design Integration Lead
Lead the end-to-end integration of high-performance networking SoCs for AWS Nitro, defining IP blocks, resolving CDC/RDC issues, and driving synthesis/timing closure with Verilog/SystemVerilog and scripting.
Amazon Senior ASIC Design Engineer, Machine Learning Acceleration
Design and optimize custom silicon for AWS machine-learning servers, implementing high-performance RTL, microarchitecture, and trade-offs to power services like Inferentia.
Amazon Senior Software Development Engineer, FPGA
Senior engineer designing and implementing FPGA-based hardware and firmware for AWS cloud servers, leading architecture, verification, and team mentorship.
Senior FPGA Engineer
Designs and debugs FPGA firmware for high-speed RF/wireless systems, including DSP, JESD204C, and 100G Ethernet, using VHDL/Verilog and Python/C/C++.
AI/ML Camera Lead Engineer
Lead the design of camera and image-processing ASIC IP blocks using RTL, synthesis, and PPA analysis, while driving GenAI tools for hardware workflows and agentic AI solutions.
Physical Design Engineer
Designs and implements ASIC physical layouts for DSP cores used in mobile, compute, and AI products, handling floorplanning through tapeout.
Power Management IC Design
Designs and verifies mixed-signal power-management ICs for compute, data center, automotive, and industrial systems using Cadence, Spectre, MATLAB, and Verilog/AMS.
SOC Architect
Designs and optimizes System-on-Chip (SoC) architectures for mobile/IoT/XR platforms, focusing on performance, power, and security trade-offs.
USB Design Verification Senior Engineer
Design verification engineer building UVM testbenches and test plans for USB controllers (USB3.2, USB2.0) to ensure compliance with industry standards.
Design Verification Engineer
Design Verification Engineer at Qualcomm verifies Bluetooth chipset designs using SystemVerilog/UVM, formal checks, and emulation to ensure hardware meets specifications before production.
Senior Logic Design Engineer
Job Details: Job Description: Join us to help build the next generation of AI hardware solutions. You will be part of a highly skilled team developing cutting-edge silicon for GenAI workloads, where we push the…