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Physical Design Engineer
Designs and optimizes the physical layout of AI hardware components to ensure performance and manufacturability.
RTL Design
Designs and verifies RTL (Register Transfer Level) logic for AI hardware accelerators using Verilog/VHDL and industry-standard EDA tools.
Memory Circuit Design
Designs memory circuits for AI hardware, focusing on performance, power efficiency, and scalability.
Physical Design Engineer
Designs and optimizes physical layouts for AI hardware components to ensure performance and power efficiency.
Physical Design Engineer
Designs and optimizes physical layouts for AI hardware accelerators using EMIR tools.
Physical Design Engineer
Designs and optimizes the physical layout of AI hardware chips, ensuring performance, power, and area constraints are met.
Physical Design
Designs and optimizes the physical layout of AI hardware components for performance and efficiency.
ASIC RTL Design Engineer
Designs and implements RTL for AI accelerators and ASICs, optimizing for performance and power efficiency.
Design Verification Engineer
Design Verification Engineer at Weekday AI: builds and validates AI hardware designs to ensure correctness and performance before tape-out.
Ingénieur DevOps F/H
Build and maintain CI/CD pipelines, automate deployments, and improve DevOps practices for data-heavy search and analytics platforms using Linux/Windows, Jenkins/GitLab CI, Ansible, Terraform, and Kubernetes.
VLSI Design Engineer
We are looking for talented and experienced VLIS Design Engineers/Micro-architects. As an VLIS Design Engineer/Micro-architect, you'll have the opportunity to design highly sophisticated, innovative new cutting…
Design Verification Engineer
Design Verification Engineer builds and runs UVM-based test environments to validate ASIC/SoC blocks, focusing on DDR memory interfaces and ensuring silicon-ready correctness using SystemVerilog and industry simulators.
Physical IC Design Engineer
Designs and implements physical IC layouts for AI/ML accelerators and storage chips, taking RTL through synthesis, place-and-route, timing closure, and tape-out using EDA tools and scripting.
ASIC/FPGA Design Engineer
Design and verify ASIC/FPGA logic for high-speed networking hardware using Verilog/SystemVerilog, and collaborate on bring-up and validation.
Staff Engineer - IC Design
Designs and implements reusable digital IP blocks (Verilog/SystemVerilog) for low-power wireless SoCs, focusing on PPA targets and AMBA/peripheral IP like SPI, UART, and DMA.
Lead Engineer – IC Design (STA Lead )
Lead a team to implement and sign off on timing constraints, synthesis, and static timing analysis for high-performance SoCs and ASICs using Cadence or Synopsys EDA tools.
Manager / Senior Manager – Design Verification
Lead a team to verify low-power wireless SoC designs using SystemVerilog/UVM, ensuring robust IP and chip-level functionality across global projects.
SOC Design Engineer
Designs and verifies System-on-Chip (SoC) subsystems using Verilog/SystemVerilog, integrating high-speed IPs like PCIe and DDR, and collaborating with verification and backend teams.
Emulation Front-End Infrastructure Engineer
Engineer scalable compilation and synthesis flows for NVIDIA’s hardware emulation platforms, using EDA tools like Synopsys and Cadence to validate complex chip designs before fabrication.
Intern - DRAM IP Circuits Design Engineer
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into…