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SoC Verification Architect
Designs and implements System-on-Chip verification environments and testbenches for AI hardware, using industry-standard methodologies and tools.
RTL Micro Architect Lead
Lead RTL microarchitecture design for GPU, DSP, and AI accelerators in complex SoCs, optimizing performance, power, and area while guiding cross-functional teams.
ASIC RTL Design Engineer
Designs and implements RTL for AI accelerators and ASICs, optimizing for performance and power efficiency.
ASIC RTL Design Engineer
Designs and verifies RTL for AI accelerators and ASICs, optimizing hardware for machine-learning workloads.
Design Verification Engineer
Design Verification Engineer at Weekday AI: builds and validates AI hardware designs to ensure correctness and performance before tape-out.
Разработчик FPGA
Разработка прошивок для ПЛИС Intel на SystemVerilog/Verilog/VHDL и цифровых электрических схем, включая поддержку серийных проектов.
Senior Design Verification Engineer, Silicon, Google Cloud
Design verification engineer building and validating custom TPU silicon for Google’s AI/ML workloads using SystemVerilog and UVM.
Hardware Engineer III
Design and optimize FPGA-based hardware for ultra-low-latency trading infrastructure, integrating Ethernet stacks and custom logic to parse and route market data efficiently.
Hardware Engineer, RTL
Design and verify digital logic for novel AI hardware using SystemVerilog, collaborating across architecture, verification, and physical design to tape out custom ASICs.
DevOps Engineer (Senior) - Bazel Monorepo
Build and optimize Bazel-based monorepo workflows for AI accelerator software/hardware, scaling CI/CD and developer tooling across Linux, macOS, and custom hardware.
Staff Analogue Designer, CMOS Modelling
Design and own full-chip mixed-signal CMOS behavioural models in Verilog-A/AMS for cryogenic quantum processors, enabling accurate simulation and tapeout decisions in IonQ’s Oxford lab.
Staff SoC Power Performance Verification Engineer
Job Description: Passionate in analyzing performance bottlenecks and driving architectural improvements? Eager to expand into building SoC platforms for performance verification analysis? Arm’s System-on-Chip (SoC)…
Design Verification Engineer
Design Verification Engineer builds and runs UVM-based test environments to validate ASIC/SoC blocks, focusing on DDR memory interfaces and ensuring silicon-ready correctness using SystemVerilog and industry simulators.
Global Advisory & Markets, GSET FPGA Engineer, Associate / Vice Preisdent, Sydney/ Hong Kong
Design and maintain ultra-low-latency FPGA platforms for equities trading systems, optimizing hardware-software interaction and order workflows in a global electronic trading environment.
PMTS, Design Verification Lead
Leads verification of next-gen RISC-V processor IP using SystemVerilog/UVM, ensuring functional correctness and silicon readiness for GlobalFoundries' semiconductor products.