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SoC FPGA Developer
Develop and verify complex SoC FPGAs for high-data-rate networking or DSP applications using VHDL, Verilog, and Xilinx tools, while collaborating on hardware/software co-design.
Business analyst application web F/H
Business analyst bridging user needs and technical teams to scope and validate web applications in sectors like healthcare, AI, and fintech, using tools like Playwright.
Senior Network Engineer
Salary: Competitive Remuneration About the Company: Our client is an industry-leader producing solutions across various development areas, including networking, and wireless technology. Their commitment to advancement…
HRBP_PT
Position Summary: Work as plant HR BP on planning, execution and development. Provide professional HR consultancy and solutions to support business strategies, drive organizational development and a high-performance…
Lead développeur fullstack Java/Angular F/H
Lead full-stack developer building a healthcare data platform for oncology research using Java/Spring, Angular, Elasticsearch, and AI tools to process unstructured medical data and enable cohort discovery.
Architecte fullstack Java/Angular F/H
Architect full-stack Java/Angular solutions for a health-data platform used in cancer research, integrating search engines, NLP, and AI to help clinicians explore patient data and build research cohorts.
Concepteur Digital Design (H/F/N)
Designs digital SoC/ASIC IP blocks and subsystems for automotive electronics, writing RTL in Verilog/VHDL and guiding physical implementation and verification flows.
SOC Physical Design Engineer
Performs physical design and development for SoCs and tapeout, executing methodologies like floor-planning, place and route, and timing/power optimization, using scripting languages (Perl, TCL, Python) to enhance project efficiency and benchmark PPA.
ASIC RTL Design Engineer
Design and integrate RTL for complex ASIC/SoC using Verilog/SystemVerilog, focusing on reset domain crossing, IP integration, and SoC architecture.
Physical Design
Physical Design Engineer implements ASIC/SoC RTL-to-GDSII flow using Cadence Innovus and Synopsys tools, driving timing closure, power optimization, and physical signoff on advanced nodes.
(Sr./Staff) SoC Design Engineer
Designs and implements video-processing and neural-processing SoC architectures in Verilog/SystemVerilog, verifies them through simulation, and programs embedded C/assembly to meet power, timing, and area targets.
(Staff/Sr. Staff) SoC Design Engineer
Designs and implements video-processing and neural-processing SoC architectures in Verilog/SystemVerilog, verifies them, and programs embedded C/assembly to meet power, timing, and area targets.
Physical Design Engineer
Designs and optimizes ASIC/SoC physical layouts using PNR, STA, and EMIR to meet PPA targets and signoff requirements.
Senior/ IC Design Engineer (Physical Design)
Designs and implements ASIC physical design flows (RTL-to-GDS) using AI-assisted EDA tools, focusing on synthesis, timing closure, and tape-out verification.
FPGA Engineer
Design and maintain FPGA firmware for aerospace systems, including SoC integration, signal processing, and space-grade communication interfaces.
Design Engineer
Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment,…
Physical Design Engineer
Designs advanced 2.5D/3D IC layouts, power grids, and high-speed interconnects for next-gen ASICs, using scripting and electrical analysis to power cloud, networking, and AI hardware.
Mixed Signal Design Verification (MSDV) Engineer
Designs and verifies mixed-signal ICs, leading pre-tapeout simulations and regressions to ensure silicon meets specs and is manufacturable.
CPU Physical Design Engineer
Designs and optimizes CPU physical layouts from RTL to GDS, using EDA tools to ensure power efficiency and timing closure for Intel’s latest processors.