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SOC Design Engineer
Designs and verifies digital logic for SoCs using VHDL/Verilog, ensuring low-power compliance and DFT readiness, with FPGA prototyping and silicon validation.
Staff Design Verification Engineer
Design verification engineer building and running SystemVerilog/UVM testbenches for DDR5/LPDDR5 memory interfaces and DFI protocols in AMD’s server products.
Principal Staff Silicon Design Engineer - DDR Verification
Lead verification of DDR5/LPDDR5 memory interfaces for server chips using SystemVerilog, UVM, and C/C++; mentor engineers and align firmware/software with hardware features.
FPGA Verification Engineer II
Design and verify next-gen FPGA devices using UVM, SystemVerilog, and AI/ML-enabled methodologies; collaborate with emulation and SoC teams.
Senior ASIC Design Engineer
Designs and implements ASIC chips in Verilog/SystemVerilog, closing timing/power goals and collaborating with verification and physical-design teams to bring silicon from RTL to production.
Embedded Solutions Intern
Intern designs FPGA-based embedded systems and writes low-level C code for Altera’s SoC devices, collaborating with hardware and software teams.
FPGA System Design Engineer
Design and optimize FPGA-based signal processing and embedded computing solutions for defense and aerospace, using RTL, DSP Builder, and embedded processors.
Senior Hardware (FPGA) Engineer
Design and implement high-performance FPGA logic for embedded machine-vision systems, including RTL coding, simulation, and vendor selection, while collaborating with hardware and software teams.
Senior Hardware Engineer
Design and integrate next-gen GPU hardware for mobile graphics, collaborating across teams to optimize power, performance, and area while ensuring high-quality delivery.
Senior FPGA Development Engineer
Designs and verifies high-performance FPGA subsystems for network test and measurement hardware using Verilog/SystemVerilog and industry-standard EDA tools.
Principal Engineer - FPGA/ASIC Design
Principal Engineer designing and verifying FPGA/ASIC solutions for Rolls-Royce engine control systems using VHDL/Verilog and DO-254 standards.
DRAM Memory Design Engineer - Principal | MTS | SMTS
Design and optimize DRAM circuits (arrays, control logic, I/O) for next-gen memory chips, using Verilog, SPICE tools, and Python/Tcl, while leading tape-outs and mentoring engineers.
Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU
Senior engineer building and improving ASIC verification infrastructure, CI/CD flows, and AI-assisted debug tools for GPU development at NVIDIA.
Security Architect
Designs and reviews secure hardware/firmware architectures for semiconductors, including cryptography, side-channel analysis, and Verilog/C/C++ implementations.
DIGITAL PHYSICAL DESIGN
Designs and tests semiconductor chip layouts for communications devices using CAD tools like Cadence and Synopsys, ensuring compliance with specs and timing closure.
Digital Design
Designs and verifies digital semiconductor IP using Verilog/System Verilog, UVM, and Python/C++; performs CDC, DFT, and static timing checks; collaborates on verification test plans.
Digital Design
Designs and verifies semiconductor logic for communication chips using Verilog/SystemVerilog, CDC tools, and emulation platforms to ensure zero-defect silicon.
Principal Staff Silicon Design Engineer - DDR Verification
Lead verification of DDR5/LPDDR5 memory interfaces for AMD server chips using SystemVerilog, UVM, and C/C++; mentor engineers and align firmware/software with hardware requirements.
Senior Manager/Deputy Director, ASIC Digital Design IP Engineering
Lead a team to design and deliver next-gen processor and SoC IP, driving RTL development, verification, and silicon execution while optimizing power, performance, and area.
ASIC Digital Design IP Engineer
Designs and implements high-performance processor cores and SoC subsystems using Verilog/SystemVerilog, driving microarchitecture, RTL, and PPA trade-offs with cross-functional teams.