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Senior Silicon Design Verification Engineer, YouTube Video Accelerators
Design Verification Engineer building custom silicon ASICs for YouTube video codecs using C/C++, HLS, SystemVerilog, and UVM to ensure hardware correctness and performance.
Senior FPGA Engineer
Designs, tests, and deploys FPGA firmware for rocket avionics systems, shepherding custom digital electronics from concept through flight operations on Relativity Space's Terran R launch vehicle.
Senior Verification and Simulation Infrastructure Engineer
Build and optimize simulation infrastructure for NVIDIA’s next-gen networking silicon, accelerating verification flows and debugging full-chip issues using SystemVerilog/UVM, Python, C/C++, and AI tools.
Mixed Signal Design Verification Engineer
Design and verify mixed-signal system-on-chip circuits for wireless applications using SystemVerilog, VerilogAMS, and Python.
Staff Design Verification Engineer, SoC and eFPGA
Staff engineer verifying next-gen eFPGA and SoC designs using UVM, SystemVerilog, and end-to-end silicon verification flows.
Principal/Staff Design Verification Engineer
Leads a team to verify complex ASIC/SoC designs for Bitcoin mining and AI cloud hardware, using UVM, SystemVerilog, and protocol knowledge (AXI, NoC, RISC-V) to ensure silicon quality.
ASIC RTL Design Engineer
Design and integrate RTL for complex ASIC/SoC using Verilog/SystemVerilog, focusing on reset domain crossing, IP integration, and SoC architecture.
RTL Micro Architect Lead
Leads microarchitecture design for GPU, DSP, and AI/ML accelerators in complex SoCs, defining RTL specs and optimizing performance, power, and area.
(Sr.) ISP RTL Design Manager
Leads a team to design and implement image signal processing (ISP) hardware using Verilog/SystemVerilog/SystemC, optimizing for power and gate count while collaborating with algorithm and system teams.
ISP RTL Design Engineer
Designs and verifies RTL implementations of image signal processing algorithms using Verilog/SystemVerilog/SystemC to optimize for power and gate count.
(Sr./Staff) ISP RTL Design Engineer
Design and implement image signal processing (ISP) algorithms into hardware using Verilog/SystemVerilog/SystemC, optimizing for power and gate count while verifying logic at ISP and system levels.
(Sr./Staff) SoC Design Engineer
Designs and implements video-processing and neural-processing SoC architectures in Verilog/SystemVerilog, verifies them through simulation, and programs embedded C/assembly to meet power, timing, and area targets.
(Sr./Staff) ASIC Design Engineer
Designs and verifies RTL in Verilog/SystemVerilog for on-chip test and diagnostic IP, integrates it into SoCs, and collaborates with analog/mixed-signal teams to detect failures.
(Staff/Sr. Staff) SoC Design Engineer
Designs and implements video-processing and neural-processing SoC architectures in Verilog/SystemVerilog, verifies them, and programs embedded C/assembly to meet power, timing, and area targets.
Firmware Software Engineer
Design and build firmware and tooling to accelerate semiconductor development, working with hardware teams on EDA, verification, and post-silicon validation using C, C++, and Python.
FPGA Engineer II (ONSITE)
Design and verify FPGA/ASIC digital circuits for aerospace/defense avionics, writing RTL in VHDL/Verilog and ensuring DO-254 compliance.
Principal Firmware Engineer
Principal firmware engineer leading FPGA development for aerospace navigation systems, defining standards and mentoring teams to ensure DO-254 compliance and high-reliability designs.
Senior Design Verification Engineer - Interconnect IP
Verify GPU memory subsystem and interconnect IP designs using SystemVerilog/UVM, testplans, and coverage-driven flows to ensure correctness and performance.
Senior/ IC Design Engineer (Physical Design)
Designs and implements ASIC physical design flows (RTL-to-GDS) using AI-assisted EDA tools, focusing on synthesis, timing closure, and tape-out verification.
Digital and Mixed Signal IC Design/DV Engineer
Design and verify mixed-signal ICs for current sensing, using RTL, SystemVerilog, VHDL, and UVM to ensure first-pass silicon success.