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Analog Designer (1 year contract)
Designs and verifies analog and digital IC layouts (PLL, DAC, VCO, etc.) using Cadence Virtuoso and Mentor Calibre, from cell-level blocks to full chip integration.
Staff DFx Methodology Architect
Architect and implement DFx (Design for Test, Debug, etc.) methodologies and RTL for AMD’s AI-focused SoCs and ASICs, ensuring power, performance, and timing targets while collaborating across global teams.
Hardware Systems Engineer - Board Design
Design and validate high-speed circuit boards and test systems for Apple’s next-gen SoCs, debugging power, signal integrity, and interface issues in the lab.
Senior CAD Software Engineer
Develops and maintains CAD software tools/automation for Microsoft’s silicon design infrastructure (RTL, verification, DFT, emulation), collaborating with hardware teams to scale solutions for SoC/IP projects.
Associate Engineer, System Design Engineering ( FPGA Design 2-4 years)
Design and implement high-performance FPGA logic for next-gen NAND Flash storage systems using Xilinx tools and RTL, while collaborating on embedded firmware and system validation.
Design Engineer
The Apple design team is looking for an experienced engineer to develop multiple IPs for Apple SoCs (in Storage, Computer Vision and RISC-V CPU domains). In this Role you will get to handle micro-architecture…
Systems Design Engineer - Memory Enablement
Design and validate memory subsystems (DDR5/LPDDR5) for x86 SoCs, running post-silicon enablement tests and debugging complex hardware issues.
FPGA Emulation Engineer
Build and debug FPGA-based emulation platforms (Synopsys HAPS) to validate complex SoC/ASIC designs and enable early software execution before silicon tape-out.
FPGA Engineer
Implement RTL designs on Xilinx FPGAs (Artix-7/Kintex) using Vivado, integrate boards/peripherals, and validate hardware with embedded teams.
Design Verification Engineer
Design Verification Engineer at Cisco in Armenia builds and runs testbenches in SystemVerilog to validate ASIC designs, debug with DVE/Verdi, and script in Tcl/Python/Perl.
Memory Circuit Design
Designs and optimizes high-performance, low-power memory circuits (SRAM/DRAM) using transistor-level design and SPICE simulations for advanced semiconductor nodes.
Physical Design Engineer (PNR)
Execute complete Place & Route flow for ASIC and SoC designs, focusing on floorplanning, power planning, and CTS using industry EDA tools to optimize chip performance and manufacturability.
Physical Design Engineer - EMIR (Route EMIR)
Design engineer runs EMIR checks (electromigration and IR drop) on advanced SoC power grids using Route EMIR, Static/Dynamic IR, Signal EM and Power EM to ensure reliable chip signoff.
RTL Design
Design and implement RTL for next-gen ASICs using Verilog/SystemVerilog, optimizing for performance, power, and area while collaborating with cross-functional teams.
Security IP Design Engineer
Designs and verifies hardware security IP for SoCs, including cryptography, key management, and secure boot, using Verilog and SystemVerilog.
Large Loss Bodily Injury Manager
National General is a part of The Allstate Corporation, which means we have the same innovative drive that keeps us a step ahead of our customers’ evolving needs. We offer home, auto and accident and health insurance,…
Security IP Verification Engineer
Design and verify security IP for SoCs, focusing on cryptography, key management, secure boot, and hardware root of trust using UVM, SystemVerilog, and C.