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Senior FPGA Architect: Quantum Hardware & Real-Time DSP
Design FPGA hardware and real-time DSP systems to control quantum computing devices, using Verilog/VHDL and collaborating across engineering teams.
2027 Shanghai FPGA Developer Summer Internship
Build ultra-low-latency trading systems using FPGA hardware, VHDL/SystemVerilog, and Python/C++ in a fast-paced quantitative trading environment.
Digital ASIC Designer (EP-ESE-ME-2026-134-GRAP)
Design a radiation-tolerant RISC-V microcontroller ASIC for CERN’s particle physics detectors using 65/28 nm CMOS, RTL-to-tapeout with fault-tolerant techniques and post-silicon validation.
Senior Memory Systems Design Engineer
Position Overview: We are seeking an experienced System Design Engineer to join our dynamic engineering team. This position offers the opportunity to work on next generation NAND Flash Storage systems, develop…
FPGA Engineer
Design and optimize FPGA/SoC solutions for high-performance digital signal processing and RF applications using Xilinx devices and Vivado.
Senior Analog-/Mixed-Signal-IC-Designer:in Automotive (m/w/d) (w/m/div.)
Design and lead Analog/Mixed-Signal ICs for automotive power and electrification ASICs, from spec to silicon, ensuring performance, reliability, and ISO 26262 compliance while coaching junior engineers.
Senior Analog/Mixed-Signal IC Designer Automotive (f/m/div.)
Designs high-performance analog/mixed-signal circuits for automotive ASICs, leading full development flow and ensuring first-pass silicon success in electrification and smart power applications.
Инженер-программист ПЛИС / FPGA Designer
Designs FPGA firmware for high-performance wireless systems, focusing on DSP algorithms, radio protocols, and high-speed interfaces using Verilog/VHDL and Xilinx tools.
Hardware Designer
Design high-speed electronic systems and PCBs for clients, collaborating with FPGA, software, and SI teams to deliver robust hardware from concept to validation.
FPGA Designer
Design and deliver FPGA-based systems using Xilinx/Intel tools, RTL/Verilog/VHDL, and collaborate across teams to close timing and debug prototypes for clients in high-speed electronics.
Senior Lead FPGA Engineer
Lead FPGA design and verification for aerospace/defense avionics, writing VHDL/SystemVerilog, ensuring DO-254 compliance, and mentoring small teams.
Lead Engineer, FPGA
Lead FPGA verification for safety-critical avionics under DO-254, defining test strategies and ensuring FAA/EASA certification readiness with UVM, SystemVerilog, and VHDL.
Silicon Design Verification Staff Engineer
Design and verify PCIe interconnect IP for AMD’s GPUs, APUs, servers, and consoles using UVM/SystemVerilog, collaborating with global teams.
Senior Physical Design Engineer
Designs and implements large SoC physical layouts from RTL to GDSII, including floorplanning, place & route, power grids, and sign-off verification for high-performance chips.
Enterprise Networking Hardware Design Engineer
Lead hardware board design for next-gen routing products, shepherding designs from architecture through production while coordinating cross-functional teams.
Senior FPGA & Imaging Systems Engineer
Design FPGA-based imaging systems for SWIR cameras, including Verilog/VHDL, DDR4, SERDES, and embedded C/C++ pipelines, while collaborating across hardware, firmware, and software teams.
Firmware Design Engineer
Design and implement embedded firmware for advanced imaging systems, integrating FPGA logic, camera sensors, and high-speed interfaces to deliver real-time imaging solutions.
Hardware Engineer - Jurong East [2683]
Designs and debugs FPGA firmware, PCB schematics, and calibration software for car-park and airport security systems using Verilog, Altium/KiCad, and C++/MFC.
R&D FPGA developer in power quality applications
Design and implement FPGA-based real-time control and signal processing for power-quality systems using VHDL/Verilog and Xilinx/Lattice tools.
FPGA Engineer II
Design and implement FPGA logic in VHDL for high-speed interfaces, RF/EO DSP, and embedded systems using AMD, Altera, and Microchip toolchains, verified with constrained-random tests.