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Amazon Software Development Engineer, Amazon Leo Optical Inter-Satellite Link
Develop flight software for satellite optical inter-satellite links, including real-time control, fault tolerance, and AI-driven recovery, targeting embedded Linux and RTOS.
Principal Engineer - Design
Leads hardware/software co-verification for SoC devices using emulators (e.g., Cadence Palladium) and FPGAs, bridging RTL porting, firmware development, and system-level testing across pre- and post-silicon phases.
Principal Electrical Engineer - Digital Circuit Card Design
Designs high-speed digital circuit boards for military radar systems using CAD tools, power/signal integrity analysis, and embedded processors; collaborates on FPGA-based designs and hardware testing.
Senior Electrical Engineer - FPGA Verification
Senior Electrical Engineer verifies FPGA-based radar designs using SystemVerilog/UVM testbenches and industry simulators, ensuring functional correctness and coverage.
Memory Validation Architect
Architect and lead validation of next-gen memory subsystems (DDR5, LPDDR5/6, HBM) for FPGAs, defining scalable methodologies and driving silicon bring-up, debug, and customer enablement.
Silicon Design Engineer
Lead verification of AMD’s IOHUB subsystem, defining test plans and closing coverage for high-performance interconnect IP used in CPUs, GPUs, and data-center hardware.
Principal Fabric/Network Architect
Principal Fabric/Network Architect designs the end-to-end data path for Neurophos’ optical AI accelerator, including RDMA transports, PCIe bridges, NICs, and HBM DMA, to scale distributed inference workloads.
Senior Firmware Development Engineer
Develop and profile firmware for next-gen AI and compute silicon powering Azure, focusing on PCIe, memory, and network workloads in embedded systems.
Hardware Engineer, FPGA
Design and verify digital logic for novel AI hardware using SystemVerilog, collaborating across RTL, verification, and physical design to tape out custom ASICs.
SOC Micro-Architect and RTL Designer
Designs and implements silicon micro-architecture and RTL for high-performance GenAI compute chips, owning subsystems from spec to tapeout and collaborating with verification and physical design teams.
Principal Technical Recruiter
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
