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Senior PCIe Bridge Design Verification Engineer
Senior engineer verifying PCIe bridge IP for Microsoft's cloud hardware, using UVM-based testbenches and generative AI to ensure quality and performance of Azure infrastructure.
Senior Fabric Design Verification Engineer
Senior engineer verifying complex chip designs for Microsoft's cloud hardware, using UVM-based test environments and AI tools to ensure quality and performance of fabric interconnects and protocols like CHI and AMBA.
Senior PCIe IP Design Verification Engineer
Senior engineer verifying PCIe IP for Microsoft’s cloud hardware, using UVM/SystemVerilog and generative AI to ensure silicon quality and performance.
Principal Design Verification Engineer- SerDes/PHY
Principal Design Verification Engineer builds and runs UVM testbenches to verify multi-Gbps SerDes/PHY IP for AI connectivity, ensuring first-pass silicon success for standards like PCIe Gen 6/7, UALink, and Ethernet.
Senior Staff Embedded Software Engineer - AI Accelerator
Lead firmware and low-level system software development for next-gen AI accelerator platforms, driving hardware-software integration, performance optimization, and reliability for cloud-scale systems.
ASIC Design Verification Engineer
Build and debug SystemVerilog/UVM testbenches for ASIC IP blocks powering 5G networks, from block-level to top-level verification and SW-driven validation.
Senior AI Engineer
Design and build confidential AI systems that run in trusted execution environments, ensuring model integrity and secure cloud-native deployment.
Modem Hardware/Baseband Engineer in Architecture & Network Solutions (Telematics) l AUMOVIO Korea
Design and validate next-gen telematics hardware and baseband systems for automotive OEMs, integrating cellular, GNSS, Wi-Fi, and Ethernet while ensuring automotive-grade reliability and compliance.
Senior Confidential AI Engineer
Design and build confidential AI systems that protect models and data using trusted execution environments, remote attestation, and secure provisioning in cloud-native and on-prem deployments.
Hardware Engineer
Design and optimize FPGA-based hardware for ultra-low-latency trading infrastructure, integrating Ethernet stacks and custom logic to parse and route exchange data efficiently.
Staff Application Engineer 高级应用工程师- 机器人硬件嵌入式解决方案 ( experienced in hardware is required )
Designs and debugs embedded hardware for robot joints, dexterous hands, and control boards using Renesas MCUs/MPUs/SOCs, including power, sensors, and industrial interfaces like EtherCAT and CAN-FD.
[AI반도체] Hardware Application Engineer
Hardware engineer optimizing NPU/SoC-based boards for edge AI devices, debugging power/interface issues, and supporting manufacturing ramp-up and customer deployments.
