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STAFF ASIC Design Engineer
Designs and implements next-gen SSD controller ASICs, writing RTL, collaborating on verification, and optimizing flows with AI-assisted tools.
Senior Packaging Technical Engineer - Hardware
Designs and implements advanced chip pad rings and package layouts for AI GPUs, collaborating with hardware teams to optimize signal integrity and power delivery.
Sr Site Reliability Engineer
Maintains and optimizes NCR Voyix’s virtual server environments, VMware infrastructure, and cloud platforms (AWS/GCP/Azure) while troubleshooting OS, networking, and storage systems for retail and dining clients.
Technical Program Manager- PDK/IP
Own and drive PDK/IP infrastructure for Cisco’s hardware platforms, coordinating vendor IPs, standard cells, and PDKs from design through tape-out and post-silicon validation.
Intern Firmware Engineer
Intern firmware engineer writing and testing embedded C/C++ code for storage devices, collaborating with teams to debug and optimize firmware for microcontrollers.
Senior RTL Design Engineer, TPU
Design and verify custom silicon for Google’s TPU AI accelerators, focusing on management/control subsystems and SoC integration.
Director, Silicon Physical Design CAD
Lead a team in Bangalore to define and scale physical design methodologies and CAD flows for Microsoft’s custom silicon (Azure Cobalt and Maia), driving AI-driven automation and first-pass silicon success.
Technical Marketing Engineer – FPGA Design
Technical Marketing Engineer creating training, documentation, and demos for AMD’s Vivado FPGA tool suite, validating features and enabling customers through clear technical communication.
Senior Technical Marketing Engineer - Vivado
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And…
Senior Analog & Mixed-Signal Layout Design Engineer
We are seeking a highly skilled High-speed SERDES IO PHY Layout designer with 5 - 9 years of experience. Apart from Serdes PHY Layout, the ideal candidate should have a strong background in analog/IO design principles,…
Circuit Design Engineer - Library
Do you want to utilize your engineering background to make big things happen? Can you influence, connect, get results and communicate effectively? Can you deliver on a predictable and dynamic schedule? Do you have a…
Physical Design Engineer
Designs and optimizes ASIC chip layouts using Place & Route tools like Cadence Innovus or Synopsys ICC2, focusing on timing, power, and area efficiency.
Principal Engineer - Design Enablement PDK cell development
Principal Engineer develops Process Design Kit (PDK) components for semiconductor fabrication, including device libraries, automation tools, and EDA-compatible tech files.
Physical Design Engineer
Lead the RTL-to-GDSII physical design flow for complex ASICs, optimizing PPA and driving tape-out while mentoring a team of engineers.