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Senior RTL Design Engineer, TPU
Design and verify custom silicon for Google’s TPU AI accelerators, focusing on management/control subsystems and SoC integration.
Senior Product Planning Engineer - Simulation, Security, and Deployment
Lead the roadmap for AMD’s FPGA/SoC simulation tools (UVM, SystemVerilog, HDL), RTL encryption, and deployment workflows, shaping verification methodologies and influencing industry standards.
Senior FPGA Engineer (DV Equities)
Design and optimize ultra-low-latency FPGA firmware for high-frequency equities and futures trading systems using Xilinx and SystemVerilog.
CPU Design Integration Engineer, Google Cloud
Design and integrate custom silicon for Google Cloud’s AI and hyperscale systems, using Verilog/SystemVerilog and scripting to ensure chip quality and performance.
Staff ASIC Digital Engineer (FPGA Prototyping, Emulation, System-Level Debugging) with 8 to 12 years of experience
Designs and debugs FPGA-based ASIC prototyping platforms, automating bring-up and co-verification between firmware and silicon for Sandisk’s pre-silicon teams.
Senior Staff VLSI Design Engineer (SystemC, Functional Modeling, C++ , Verification)
Leads VLSI design and verification for memory systems, writing C++/SystemC models, testbenches, and debugging firmware issues while mentoring junior engineers.
Staff VLSI Design Engineering (SOC Verification, System Verilog, UVM)with 8 to 12 years of experience
Lead verification of complex SoC designs using SystemVerilog, UVM, and formal tools; mentor teams and drive silicon success.
Technical Marketing Engineer – FPGA Design
Technical Marketing Engineer creating training, documentation, and demos for AMD’s Vivado FPGA tool suite, validating features and enabling customers through clear technical communication.
Lead Design Verification Engineer
Design and implement verification environments for AMD’s Network-on-Chip IPs and SoCs using SystemVerilog/UVM, formal tools, and coverage-driven flows to ensure functional correctness.
Senior Silicon Design Verification Engineer
Design and verify custom silicon for Google’s devices, building UVM testbenches and formal verification flows to ensure ASICs meet performance and reliability targets for AI and image-processing hardware.
Principal Engineer- Digital Design
Lead the architecture and RTL design of high-speed switching fabrics for next-gen memory and AI interconnects, guiding teams from spec to silicon bring-up.
Senior/Staff Front-End Engineer (RISC Processor Integration)
Integrate RISC processors (RISC-V/Arm) into SoC platforms, configure subsystems, and collaborate on RTL, firmware, and system bring-up for Bitdeer’s Bitcoin mining and AI cloud hardware.
Research Assistant (IC Design and EDA)
Research Assistant designs and evaluates open-source RISC-V processors and AI accelerators using Verilog/SystemVerilog and EDA tools, aiming to publish findings in top-tier venues.
Junior Digital Design Engineer
Designs and verifies digital sub-circuits for high-performance micro-controllers using Verilog/SystemVerilog, synthesis, and formal verification, collaborating with analog and software teams.
Physical Design Engineer Intern
Internship assisting in the design and physical implementation of digital and mixed-signal ICs for power management and signal functions using ASIC tools like synthesis and P&R flows.
Senior FC Verification & Simulation Infrastructure Engineer
Build and optimize simulation infrastructure for NVIDIA’s next-gen networking silicon, accelerating full-chip verification with SystemVerilog/UVM, Python, C/C++, and AI tools.
Logic Designer and FPGA Tech Lead
Lead FPGA architecture and RTL development for real-time medical systems, guiding Verilog/SystemVerilog implementations, timing closure, and hardware bring-up in a regulated healthcare environment.
Senior Design Engineer - Security IP
Designs and verifies hardware security IP for SoCs, including cryptography, key management, and secure boot, using Verilog and scripting.