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Front End CAD Engineer
Develop and optimize front-end EDA workflows for ASIC/SoC design using Verilog, SystemVerilog, and scripting languages like Python and Perl.
Инженер-разработчик встраиваемых систем / Инженер-электроник
Разрабатывает встраиваемое ПО для микроконтроллеров и UEFI BIOS, отлаживает радиоэлектронную аппаратуру и протоколы взаимодействия устройств на C, STM32 и x86-64.
Senior Silicon Physical Design Engineer, Google Cloud
Designs and optimizes custom silicon for Google Cloud, focusing on performance, power, and area while collaborating with cross-functional hardware teams.
Hardware Engineer
Design and optimize FPGA-based hardware for ultra-low-latency trading infrastructure, integrating Ethernet stacks and custom logic to parse and route exchange data efficiently.
Senior AI/ML Engineer
Build and deploy AI agents that automate silicon IP design workflows using RAG, structured tool execution, and EDA tool integration to accelerate spec-to-netlist cycles.
[AI반도체] SoC Design Engineer
Designs and verifies RTL for AI NPUs, focusing on SoC blocks like interfaces, power management, and clocking using Verilog/SystemVerilog and scripting (Python/Tcl).
FPGA Developer
Design and implement FPGA-based digital logic using VHDL/Verilog, integrate custom IP cores, and optimize designs for performance and timing closure.
Sr Principal Engineer Design, CPU Microarchitecture & RTL Design
Lead the microarchitecture and RTL design of next-gen AI-enabled RISC-V CPU cores, including vector/matrix processing engines, while balancing performance, power, and area constraints.
Senior Hardware Engineer
Senior Hardware Engineer designs and validates sports-tech hardware (PCBs, RF, FPGA) to ensure measurement accuracy and reliability for global athletes.
FPGA Engineer I
Design and verify FPGA logic in VHDL for defense systems, using tools like Xilinx Vivado and Altera Quartus, and support lab integration and documentation.
Senior Engineer, Design Automation Methodologies
Designs and automates ASIC front-end methodologies for IP/SoC projects, using EDA tools like SpyGlass and scripting in Python/Perl/TCL to improve design checks and integration flows.
Senior Subsystem Design Verification Engineer
Design and verify complex silicon subsystems for Arm-based platforms using SystemVerilog/UVM, ensuring functionality, performance, and coverage closure.
Junior Digital Design/DfT Engineer
Designs and verifies digital circuits for IoT and automotive chips using VHDL/Verilog, SystemVerilog, and Python, with a focus on signal processing and embedded software integration.
Lead Design Verification Engineer
Lead pre-silicon verification of semiconductor IPs and SoCs using UVM, SystemVerilog, and industry simulators to ensure functional correctness before tape-out.
Graduate Talent FPGA IP Software Development
Graduate trainee develops FPGA IP cores using HDL, RTL design, and verification, working with tools like Vivado/Quartus and collaborating on real-world FPGA-based system projects.