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Leads a Shanghai hardware design team to develop high-speed Active Electrical Cables and Smart Cable Modules for AI infrastructure, while providing local customer engineering support to China-based hyperscalers and OEMs.
Lead a new Taiwan hardware engineering hub to design validation platforms and rack-scale systems for AI connectivity, while partnering with OEMs across Asia to integrate Astera Labs’ silicon into their products.
Lead a hardware engineering team at a NASDAQ-listed AI connectivity company, designing high-speed cables, modules, and rack-scale systems while enabling OEM customers to integrate Astera Labs' silicon into their products.
Leads hardware manufacturing and operations for AI connectivity products, partnering with Asian contract manufacturers to scale production of cables, modules, and chassis systems while optimizing quality, cost, and time-to-market.
Hardware Lab Engineer at Astera Labs in San Jose sets up and maintains test environments for silicon validation of AI connectivity solutions like PCIe, CXL, and Ethernet, using high-speed test equipment and Python automation.
Junior engineer builds and runs test environments to verify next-gen AI connectivity chips using SystemVerilog/UVM and debugs hardware issues with design teams.
Lead firmware QA testing for PCIe-based connectivity solutions, validating hardware and software integration with automation and protocol analysis in Bangalore.
Leads a team of engineers to design advanced semiconductor packages (FCBGA/FCCSP, chiplet-based) for AI connectivity solutions, collaborating with OSATs and cross-functional teams using Cadence Allegro APD/SiP.
Manages a team of physical design engineers in Toronto to implement high-speed connectivity ASICs for AI infrastructure, using advanced EDA tools and TSMC nodes.
Leads optical and electro-optical testing for high-bandwidth CPO modules and optical engines in AI and data centers, designing test hardware/software and driving yield improvements.
Principal engineer leads the design and development of advanced photonic packaging solutions for silicon photonics modules, integrating optics, electronics, and thermal systems to enable next-gen data center connectivity.
Designs and implements high-performance semiconductor chips for AI infrastructure, focusing on physical design flows, signoff, and automation in advanced process nodes.
Student role assisting senior engineers with physical design tasks for cutting-edge AI semiconductor chips, including synthesis, floorplanning, and verification using industry-standard EDA tools.
Principal Design Verification Engineer at Astera Labs designs and verifies advanced ASICs for AI infrastructure using SystemVerilog, UVM, and scripting languages, ensuring robust connectivity solutions for server and networking applications.
Principal Digital Design Engineer at Astera Labs designing high-performance AI connectivity silicon, owning RTL implementation through silicon bring-up for PCIe, CXL, and other protocols.
Principal Digital Design Engineer at Astera Labs designing high-performance connectivity solutions for AI infrastructure, using RTL, synthesis, and advanced CMOS nodes.
Principal Physical Design Engineer (STA) at Astera Labs designs and optimizes timing for high-performance connectivity ASICs used in AI infrastructure, leveraging advanced EDA tools and TSMC 7nm processes.
Designs power delivery systems and PCB layouts for ASIC-based AI connectivity hardware, using Cadence OrCAD/Allegro and collaborating with cross-functional teams.
Principal Product Manager at Astera Labs in San Jose defines and drives the Smart Cable Modules product line, collaborating with hyperscalers to deliver high-bandwidth connectivity solutions for AI and cloud infrastructure using PCIe, Ethernet, CXL, and related technologies.
Principal Test Engineer at Astera Labs designs and implements automated test solutions for high-speed mixed-signal silicon SoC products, using protocols like PCIe, Ethernet, and DDR, and oversees production ramp.
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