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Senior software engineer building diagnostics and manufacturing tools for high-speed datacenter hardware, using Python and embedded/Linux systems to validate and bring up AI connectivity boards.
Develops and debugs firmware for Ethernet retimers in AI infrastructure, troubleshooting link failures and integrating new products from silicon bringup to deployment.
Designs and implements firmware for Astera Labs' AI connectivity hardware, focusing on SoC subsystems and high-speed interfaces like PCIe and Ethernet.
Senior Principal Digital Design Engineer at Astera Labs in San Jose, CA, leading architecture and RTL implementation for AI connectivity chips using PCIe, CXL, UALink, Ethernet, and DDR protocols.
Leads end-to-end execution of advanced-node ASIC products from concept to production, managing schedules, budgets, and cross-functional teams to deliver revenue-critical silicon on time and at scale.
Leads the product strategy for a unified management suite that orchestrates software, firmware, and silicon across Astera Labs' AI connectivity products, focusing on PCIe, CXL, and Ethernet technologies.
Designs and implements top-level physical design for AI-focused semiconductor chips, collaborating with cross-functional teams to meet strict performance, power, and area targets.
Designs and automates chip design flows for semiconductor connectivity solutions, using Python, Tcl, and EDA tools to optimize RTL generation and hardware development.
Designs and implements advanced semiconductor packages for high-performance AI connectivity chips, collaborating with teams to optimize electrical, thermal, and mechanical performance from concept to production.
Senior/Staff STA Engineer at Astera Labs in Israel designs and signs off timing for high-performance AI connectivity chips, using EDA tools and SDC constraints to meet aggressive data-center targets.
Leads the full lifecycle of ASIC chip development for AI infrastructure, coordinating cross-functional teams to design, fabricate, and validate semiconductor solutions.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
Designs power integrity and electromigration checks for AI-focused semiconductor chips, using tools like Ansys RedHawk and Cadence Voltus to ensure reliability in advanced FinFET nodes.
Principal Architect at Astera Labs in Tel Aviv designs high-performance AI connectivity solutions, focusing on PCIe, Ethernet, and advanced interconnect protocols like CXL and UALink.
Designs and implements verification environments for high-performance semiconductor chips in AI infrastructure, using SystemVerilog/UVM to validate digital blocks and subsystems.
Designs and automates semiconductor chip implementation flows, focusing on parasitic extraction and GenAI-driven methodologies to optimize high-speed AI connectivity chips from RTL to GDSII.
Designs power integrity and electromigration solutions for high-performance AI chips, ensuring voltage stability and reliability in advanced semiconductor nodes.
Leads engineering operations and ASIC tapeout management for a semiconductor company, driving decision velocity and execution rigor in San Jose, CA.
Leads the design and implementation of high-performance digital circuits for AI connectivity chips, using PCIe, CXL, Ethernet, and DDR protocols, from architecture to silicon bring-up.
Junior Physical Design Engineer at Astera Labs in Tel Aviv builds and optimizes semiconductor chips for AI infrastructure, focusing on physical implementation, signoff, and automation using RTL-to-GDS flows and EDA tools.
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