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Senior Design Engineer - Security IP
Designs and verifies hardware security IP for SoCs, including cryptography, key management, and secure boot, using Verilog and scripting.
Chip/Software Engineer
Builds AI-native EDA tools and agent-driven workflows for chip design, writing Python/C++ code for Fortune enterprises and chip unicorns while translating user feedback into product updates.
Staff FPGA Design Engineer
Staff FPGA Design Engineer leading architecture, RTL development, verification, and flight-readiness of FPGA-based avionics subsystems for satellites using SystemVerilog/VHDL, Microchip Polarfire, and AMD Zynq/Versal FPGAs.
Firmware Engineer
Design and implement FPGA firmware for next-gen radar and sensing systems, integrating with software and hardware for defense and commercial applications.
FPGA Engineer
Design and implement FPGA-based digital signal processing for next-gen radar and sensing systems, integrating with software and hardware in a defense-focused product company.
Sr. FPGA Engineer
Design and implement FPGA-based signal processing for next-gen radar and sensing systems, integrating with software and hardware in a defense-focused R&D environment.
FPGA Engineer
Designs and verifies FPGA-based digital circuits for automated trading systems, develops reusable IP, and integrates hardware with software stacks using SystemVerilog/Verilog/VHDL and C++.
RTL Design Technical Lead, Networking, Google Cloud
Leads RTL design for Google’s custom silicon solutions, focusing on ASIC development for SoC/VLSI, Verilog/SystemVerilog coding, and hardware-software integration to power Google Cloud and consumer products like Vertex AI.
Logic Design Engineer
Logic Design Engineer Location: Israel - Haifa (IL) Description Chips Talk, We Listen proteanTecs is a game-changing startup that's giving advanced electronics the power to report on their own health. In a digital…
Senior FPGA Design Engineer / Hardware Engineer
Design and optimize FPGA systems to reduce latency and boost throughput for a proprietary trading firm, using SystemVerilog and automated verification.
Lead RTL Design Engineer
Lead the RTL design and microarchitecture of an ultra-low-power SoC for edge AI/IoT, defining dataflow fabrics, memory subsystems, and interconnects using SystemVerilog and collaborating across hardware, firmware, and verification teams.
Senior Design Engineer, Networking, Google Cloud
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…
RTL Design Engineer, TPU and ML
Designs and verifies custom silicon for Google’s TPU AI accelerators, focusing on high-performance RTL code and cross-functional integration with verification and physical design teams.
Senior FPGA Team Lead
Lead a team to architect and implement FPGA-based signal processing systems for a space-based cellular broadband network, using VHDL/Verilog and Xilinx tools.
ASIC Design and Integration Engineer – Silicon Security
Design and integrate secure ASIC subsystems to protect Apple’s SoCs from side-channel attacks and ensure data integrity using RTL, UPF, and cryptographic engines.
ASIC Design Verification Engineering Leader
Lead verification of Cisco’s cutting-edge data-center ASICs, building DV environments, writing test plans, and ensuring full coverage with Verilog/SystemVerilog/UVM while collaborating with designers and software teams.
Silicon Design Engineer - RTL Integration
Designs and integrates RTL components for next-gen FPGA and programmable SoC products, ensuring full-chip connectivity and architectural alignment while improving development efficiency.