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Physical Design Engineer
Design and implement complex ASIC/SOC physical layouts using Synopsys tools like Fusion Compiler or ICC2, debug timing/congestion issues, and mentor junior engineers.
FPGA Design Engineer
Designs, implements, and tests FPGA firmware for high-speed electric compressors used in aerospace and heat pumps, using VHDL and Xilinx tools.
Lead Silicon Design Engineer - RTL
Lead RTL design engineer at AMD, coding Verilog/SystemVerilog IP cores for networking, security and storage ASICs while collaborating across global teams.
Senior/Staff Front-End Engineer (SOC)
Design and implement Verilog RTL for SoC blocks, integrate IPs, and optimize performance through synthesis, timing closure, and power reduction in a semiconductor R&D team.
Physical Design - SOC Top Lead
Lead the physical design and tapeout of energy-efficient AI/ML SoCs, integrating blocks, timing, power, and signal integrity to deliver GDS-ready chips using advanced finfet nodes.
Design-for-Test (DFT) Engineer-Singapore
Design-for-Test engineer implements chip-level testability features (scan, MBIST, ATPG) and debugs DFT-related timing/power issues to ensure silicon test success.
Physical Design Engineer -Singapore
Designs chip layouts from netlist to GDSII, optimizing PPA and ensuring physical verification/STA/IREM signoff for advanced process nodes.
Staff Silicon Design Engineer (DFT)
Lead a team to design and implement test strategies (Scan, MBIST, iJTAG) for AMD’s latest AI and data-center chips, ensuring robust production testing and yield optimization across ASIC/FPGA designs.
Design Verification Engineer
Design Verification Engineer at Texas Instruments in Knoxville builds and runs test benches to verify analog and mixed-signal ICs, ensuring first-pass silicon success for industrial, automotive, and consumer applications.
Analog Design Engineer- eInfochips
Designs high-performance analog/mixed-signal circuits (PLLs, ADCs/DACs, RFIC) using Cadence Virtuoso, Spectre, and Mentor Calibre, with multi-node process experience from 28nm to 7nm.
Design Engineer -Memory Layout
Job Overview: This opening is for a memory layout designer in our PHYSICAL IP – MEMORY group in Noida. We work on innovative memory architectures in pioneering technology nodes to enable the best Arm Systems in all the…
Senior FPGA Engineer
Designs and verifies high-performance FPGA and SoC solutions in VHDL/Verilog, integrating IP and optimizing timing for mission-critical applications.
IC package design engineer
Job Description Meet the Team Join the Package Design Team at Cisco Silicon One in Armenia, a group leading the way in developing Cisco's groundbreaking silicon solutions for next-generation networking. As a…
Design Verification Engineer
Design Verification Engineer builds and runs test environments for complex ASIC and mixed-signal IP using SystemVerilog/UVM, coverage analysis, and debug to ensure correctness before tape-out.
Senior/ IC Design Engineer (Physical Design)
Designs and implements ASIC physical design flows (RTL-to-GDS) using EDA tools and AI-assisted methodologies to optimize PPA and timing for tape-out.
Technical Staff Engineer - Design
Designs IO pad rings, bump patterns, and connectivity for advanced SoC storage/memory controllers using EDA tools and scripting.
Physical Design Engineer
Designs and optimizes advanced ASICs for Cisco’s networking hardware, using EDA tools like Innovus and Tempus to perform RTL-to-GDSII flows, timing closure, and power integrity analysis.