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Design Verification Engineer
Design Verification Engineer at Texas Instruments in Knoxville builds and runs test benches to verify analog and mixed-signal ICs, ensuring first-pass silicon success for industrial, automotive, and consumer applications.
SOC Design Verification Engineer
Designs and runs SystemVerilog/UVM testbenches to verify Arm-based CPUs, PCIe, DDR, and SoC subsystems, writing C/C++/Assembly tests and debugging RTL issues.
Designer, Systems (Computer)
Designs and implements high-performance RISC-V CPU and SoC RTL modules using SystemVerilog, collaborating with architects, verification, and backend teams to optimize performance, power, and area.
Senior RTL Design Engineer – PCIe Subsystems
Designs and implements PCIe subsystems for next-gen infrastructure SoCs using SystemVerilog/Verilog, collaborating with verification and implementation teams to ensure tape-out readiness.
Design Verification Engineer
Design Verification Engineer builds and runs test environments for complex ASIC and mixed-signal IP using SystemVerilog/UVM, coverage analysis, and debug to ensure correctness before tape-out.
Senior/ IC Design Engineer (Physical Design)
Designs and implements ASIC physical design flows (RTL-to-GDS) using EDA tools and AI-assisted methodologies to optimize PPA and timing for tape-out.
MTS, AI Optimized Memory Digital Design Engineer
Designs high-performance memory systems for AI workloads using SystemVerilog RTL, synthesis, and PPA analysis to balance performance, power, and area from concept to silicon.
Member of Technical Staff - Design Verification
Leads hardware verification for AI-generated chip designs, ensuring rigorous validation of custom ASICs at tapeout stage using SystemVerilog, UVM, and Python, while collaborating with AI/ML and architecture teams to refine verification strategies and methodologies.
Senior ASIC Design Verification Engineer, Compute DSP/AI Processors
Designs and verifies ASIC IP for Qualcomm’s Snapdragon DSP/NPU, using UVM and SystemVerilog to accelerate AI and video workloads in connected devices.
AI Automation Engineer, Staff
Build AI-driven tools to automate RTL front-end design flows using agentic frameworks like LangChain/CrewAI, reducing manual effort in synthesis, STA, and verification.
Video Codec Design Engineer
Video Codec Design Engineer, up to Staff Location: Taipei, Taipei City, Taiwan Department: ASICS Engineering Work Location: onsite Company: Qualcomm Semiconductor Limited Job Area: Engineering Group, Engineering Group…
Emulation Hardware Engineer, Google Cloud
Develop and maintain emulation models and infrastructure for Google’s custom silicon, scripting automation and debugging hardware flows to accelerate product development.
Embedded C++ Engineer (SystemC / Virtual Prototyping)
Builds virtual hardware prototypes in C++/SystemC to model SoCs and accelerate firmware development for next-gen chips like AI accelerators and consumer devices.
Senior Design Verification Engineer
Design verification engineer building and debugging SystemVerilog/UVM testbenches for custom AI silicon IP and SoCs, ensuring functionally correct RTL before tape-out.
TPU Hardware Design Engineer, Cloud
Designs and verifies custom silicon for Google’s TPU AI accelerators, focusing on microarchitecture, RTL coding, and integration with AI/ML systems.
Senior FPGA / Radar Systems Engineer — Berlin, Germany
Senior FPGA engineer building real-time radar, GPR and SAR systems in Berlin, integrating high-speed ADCs, RF frontends and embedded Linux on Xilinx/AMD platforms.