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Technical Staff Engineer - Design
Designs IO pad rings, bump patterns, and connectivity for advanced SoC storage/memory controllers using EDA tools and scripting.
Physical Design Engineer
Designs and optimizes advanced ASICs for Cisco’s networking hardware, using EDA tools like Innovus and Tempus to perform RTL-to-GDSII flows, timing closure, and power integrity analysis.
Principal Engineer - Analog Design
Designs and validates high-speed analog and mixed-signal IP blocks (PLLs, ADCs, DACs, filters) for multi-GHz timing products using Cadence tools and Verilog-A modeling.
Инженер-разработчик ПЛИС (FPGA designer)
Обязанности: Разработка и отладка проектов для ПЛИС. Документирование разработанных проектов. Требования: Высшее (техническое) образование, предпочтительно-в области радиотехники. Опыт работы от 3-х лет в разработке и…
Senior Design Engineer
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into…
Software Engineer III, Embedded Systems and Firmware, Audio
Develops embedded firmware and audio algorithms for Google Pixel earbuds, integrating signal processing and acoustics to enhance hearing and speech features.
WLAN RTL Design Senior Engineer
Designs next-gen WLAN hardware at the RTL/IP level, focusing on logic synthesis, timing constraints, and low-power optimization for 6nm+ processes using tools like Genus, Primetime, and Tcl scripting.
Implementation Timing / STA Design Engineer
Implementation Timing / STA Design Engineer Location: San Diego, California, United States of America Department: ASICS Engineering Work Location: onsite Company: Qualcomm Technologies, Inc. Job Area: Engineering…
Staff Design Verification Engineer
Design verification engineer building UVM testbenches for high-speed interconnects (PCIe, CXL, AXI) to ensure ASIC/subsystem correctness before tape-out.
Silicon Physical Design STA Lead, Google Cloud
Lead a team to perform Static Timing Analysis (STA) on Google’s custom silicon SoCs, ensuring timing closure and low power for AI accelerators while collaborating with architecture and physical design teams.
Staff Test Engineer
Designs and executes test plans for GPON/XGS-PON broadband hardware, validating L2/L3 protocols and OLT/ONT devices using Python automation and tools like Spirent/Ixia.
Senior Engineer, IC Package Design
Senior Engineer plans, coordinates, and executes IC package design programs from feasibility through manufacturing, driving clarity and reducing execution risk while collaborating with cross-functional teams.
Physical Design Engineer
Designs and optimizes digital ASIC layouts from netlist to GDSII using EDA tools like Synopsys ICC2 or Cadence Innovus, scripting in Python/TCL, and exploring AI-assisted flows for advanced process nodes (TSMC N5/N4P/N3).
Senior Physical Design Engineer
Senior Physical Design Engineer at Qualcomm leading floorplanning, placement, and timing closure for high-speed digital blocks on advanced nodes (TSMC N5/N4P/N3) using Synopsys ICC2, Cadence Innovus, and AI-assisted EDA flows.
CPU Physical Design Engineer
Designs and optimizes CPU physical layouts using Place & Route tools (FC/Innovus), STA (Primetime/Tempus), and UPF/CPF for low-power, high-speed ASICs.
Emulation Hardware Engineer, Google Cloud
Develop and maintain emulation models and infrastructure for Google’s custom silicon, scripting automation and debugging hardware flows to accelerate product development.
Senior Engineer, Systems Design Engineering
Designs and troubleshoots hard-disk-drive systems, analyzing failures in electromechanical, firmware, and media components to improve yield and quality.
Circuit Design Engineer, Technology and Foundry Interface, Google Cloud
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…