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Director, ASIC Design & Front-End Implementation
Lead a team designing and implementing next-generation networking ASICs, guiding RTL development, implementation, and tapeout while collaborating with cross-functional teams to meet performance and schedule targets.
Director, ASIC Design & Front-End Implementation
Lead a team designing and implementing high-performance networking ASICs from architecture to tapeout, collaborating with cross-functional teams to deliver silicon for HPE's networking products.
Senior EDA Tools Software Engineer
Build and lead a new automation platform for SoC chassis design, translating architecture specs into generated RTL, registers, and verification collateral using Python and templating systems.
Staff Silicon Design Engineer
Design engineer verifies next-gen ASIC and FPGA SoCs using SystemVerilog/UVM, debugging failures and ensuring functional coverage for AMD’s high-performance computing and AI products.
Hardware Engineer Intern
Hardware Engineer Intern contributing to FPGA development and hardware improvements at a global trading firm, using VHDL/Verilog and collaborating with trading and tech teams.
Senior Design Engineer
Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.…
Formal Verification Architect
Lead formal verification for AMD’s I/O and SoC designs, defining methodologies and mentoring engineers to ensure silicon quality for next-gen processors and AI systems.
PLL Design Engineer
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And…
TPU PCIe RTL Design Engineer
Designs and verifies PCIe subsystems and SoC infrastructure for Google’s next-gen TPUs, focusing on high-performance AI hardware acceleration.
Principal Digital Design Engineer
Principal engineer leads a small team designing high-performance FPGA/ASIC Front Haul Gateway solutions for cellular infrastructure radios, using Verilog, SystemVerilog, and AMD Vivado tooling.
Junior SoC IP Design Engineer, Google Cloud
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…
PRINCIPAL DIGITAL BACK END ENGINEER - CORK CITY - IRELAND
Principal digital back-end engineer designs and verifies ASIC flows using Cadence tools, focusing on RTL, synthesis, timing, and physical design for high-performance semiconductor IP.
AI Chip Backend Design Engineer
Designs and evaluates backend integrated circuits for AI processors, using EDA tools and circuit simulation to optimize performance.
AI & Data Analytics Automation engineer/SG
Build Python automation tools and AI-driven productivity solutions (LLMs, RAG) to analyze semiconductor engineering data and optimize workflows.
Software Engineer - AI & Data Analytics Automation
Build Python automation, AI-assisted tools, and data analytics dashboards for semiconductor test workflows, using LLMs, RAG, and AI agents to improve engineering productivity.
Senior Verilog RTL Engineer - SoC Frontend
Implement Verilog RTL for SoCs, integrate IPs, and debug designs for a Bitcoin mining and AI cloud company.
SOC Frontend Integration Engineer
Integrate RTL blocks into top-level SoC designs using Verilog/SystemVerilog, run lint/CDC checks, and hand off to downstream teams for physical design and verification.
Senior Design Verification Engineer - Data Fabric Systems
Senior engineer verifying next-gen microprocessor interconnects using SystemVerilog/UVM testbenches and industry tools to ensure functionality and performance before silicon tape-out.