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Student role assisting senior engineers with physical design tasks for cutting-edge AI semiconductor chips, including synthesis, floorplanning, and verification using industry-standard EDA tools.
Principal Design Verification Engineer at Astera Labs designs and verifies advanced ASICs for AI infrastructure using SystemVerilog, UVM, and scripting languages, ensuring robust connectivity solutions for server and networking applications.
Principal Physical Design Engineer (STA) at Astera Labs designs and optimizes timing for high-performance connectivity ASICs used in AI infrastructure, leveraging advanced EDA tools and TSMC 7nm processes.
Principal Test Engineer at Astera Labs designs and implements automated test solutions for high-speed mixed-signal silicon SoC products, using protocols like PCIe, Ethernet, and DDR, and oversees production ramp.
Designs high-performance digital blocks for AI infrastructure chips, using Verilog/SystemVerilog and EDA tools to solve data bottlenecks in semiconductor connectivity solutions.
Senior Data Science Engineer at Astera Labs in Haifa designs and deploys data pipelines, analyzes high-speed interface performance, and builds predictive models using Python, ML frameworks, and visualization tools to optimize AI infrastructure.
Senior engineer builds and runs test environments to verify high-performance AI connectivity chips using SystemVerilog/UVM, ensuring flawless silicon for next-gen data centers.
Senior software engineer building diagnostics and manufacturing tools for high-speed datacenter hardware, using Python and embedded/Linux systems to validate and bring up AI connectivity boards.
Develops and debugs firmware for Ethernet retimers in AI infrastructure, troubleshooting link failures and integrating new products from silicon bringup to deployment.
Designs and implements firmware for Astera Labs' AI connectivity hardware, focusing on SoC subsystems and high-speed interfaces like PCIe and Ethernet.
Designs and automates chip design flows for semiconductor connectivity solutions, using Python, Tcl, and EDA tools to optimize RTL generation and hardware development.
Senior/Staff STA Engineer at Astera Labs in Israel designs and signs off timing for high-performance AI connectivity chips, using EDA tools and SDC constraints to meet aggressive data-center targets.
Designs and implements verification environments for high-performance semiconductor chips in AI infrastructure, using SystemVerilog/UVM to validate digital blocks and subsystems.
Designs and automates semiconductor chip implementation flows, focusing on parasitic extraction and GenAI-driven methodologies to optimize high-speed AI connectivity chips from RTL to GDSII.
Junior Physical Design Engineer at Astera Labs in Tel Aviv builds and optimizes semiconductor chips for AI infrastructure, focusing on physical implementation, signoff, and automation using RTL-to-GDS flows and EDA tools.
Principal Optical Test Engineer at Astera Labs designing and executing test strategies for next-gen Co-Packaged Optics (CPO) solutions, integrating silicon photonics and high-speed optical modules for AI and hyperscale data centers.
Leads validation and characterization of advanced photonic integrated circuits (PICs) integrated with electronic ICs for high-speed data center and AI applications, using optical and electrical testing tools.
Designs high-performance digital IP for AI connectivity chips, focusing on RTL, synthesis, and integration of processor and peripheral IPs at advanced semiconductor nodes.
Leads SoC design for high-performance connectivity chips, owning RTL, synthesis, timing closure, and pre/post-silicon debug at advanced process nodes using Synopsys/Cadence tools.
Leads timing closure and sign-off for high-speed connectivity ASICs at Astera Labs, using advanced STA tools and methodologies for 7nm+ SoCs in AI infrastructure.
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