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ASIC/FPGA Design Engineer
Design and verify ASIC/FPGA logic for high-speed networking hardware using Verilog/SystemVerilog, and collaborate on bring-up and validation.
Principal Engineer, Project Management - Chip Design
Lead the full lifecycle of NVIDIA’s next-gen switch ASICs, coordinating RTL design, verification, physical design, and post-silicon bring-up with cross-functional teams.
Staff Engineer - IC Design
Designs and implements reusable digital IP blocks (Verilog/SystemVerilog) for low-power wireless SoCs, focusing on PPA targets and AMBA/peripheral IP like SPI, UART, and DMA.
SOC Design Engineer
Designs and verifies System-on-Chip (SoC) subsystems using Verilog/SystemVerilog, integrating high-speed IPs like PCIe and DDR, and collaborating with verification and backend teams.
Senior Mixed Signal Design Engineer
Design and verify mixed-signal ASICs and ROICs for image sensors, including analog signal chains, low-power ADCs, and system-level simulations using Cadence, MATLAB, and Python.
Senior Principal Mixed Signal Design Engineer (Hybrid)
Lead mixed-signal IC design for advanced image sensors, guiding teams through full ASIC/ROIC development from architecture to validation in a hybrid role.
Electronics Design Engineer
Job Summary The Electronics Design Engineer will work with the software manager to advance the Vertiv management platforms by: Creating technical documentation leading to physical electronic hardware Develop design…
AI/ML driven ASIC Design and Implementation Automation Engineer
Design AI/ML-driven automation for ASIC chip development, using GenAI, reinforcement learning, and neural networks to optimize power, performance, and area for NXP’s processors.
Senior Hardware Security Engineer
Design and verify secure hardware for space systems, assess FPGA/ASIC vulnerabilities, and develop guidance to mitigate threats in embedded and cyber-physical systems.
Firmware Engineer
Develop FPGA firmware in Verilog for high-precision sensor tech used in surgical robots and industrial equipment, implementing signal-processing algorithms and low-latency communication protocols.
Senior ASIC Physical Design Engineer, Cache Coherent Interconnects
Senior ASIC engineer designing on-chip interconnects and last-level caches for NVIDIA’s CPU and AI platforms, focusing on synthesis, timing closure, and performance optimization.
Emulation Front-End Infrastructure Engineer
Engineer scalable compilation and synthesis flows for NVIDIA’s hardware emulation platforms, using EDA tools like Synopsys and Cadence to validate complex chip designs before fabrication.
Intern - DRAM Design Engineer
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into…
Intern - DRAM IP Circuits Design Engineer
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into…
PMTS ASIC Digital Design IP ENGINEERING
Designs and implements high-performance processor cores and SoC subsystems using Verilog/SystemVerilog, driving microarchitecture, RTL coding, and PPA optimization from concept to silicon bring-up.
Sr Mgr/Dep Director ASIC Digital Design IP ENGINEERING
Leads a team to design and tape out next-gen processor and SoC IP, guiding RTL development, verification, and PPA optimization for high-performance, low-power ASICs.
FPGA Engineer Engineer (eInfochips)
Designs and implements FPGA logic using Verilog/SystemVerilog, PCIe, AXI/APB interfaces, and front-end verification tools for high-speed hardware projects.
Senior Software Engineer, Hardware Tools and Methodology Development
Develops C++ tools and automated workflows for RTL generation and ASIC design at NVIDIA, improving Verilog RTL quality and connectivity algorithms for GPU and AI hardware.
Amazon Design for Test Engineer
Design for Test (DFT) Engineer at Amazon’s Annapurna Labs, building and verifying custom silicon for AWS. Uses Verilog, SystemVerilog, UVM, and scan/debug flows to ensure chip reliability and yield.
Amazon Software Development Engineer, CPLD/FPGA
Develops and maintains programmable logic (CPLD/FPGA) for AWS server designs, using Verilog/VHDL and embedded C/C++ to optimize cloud infrastructure hardware.