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Extreme Networks
3 weeks ago

Quality Assurance Engineer

HybridAPACContract
India

Software/Senior/Staff QA Engineer Team: Engineering Location: Chennai, India Commitment: Fulltime Workplace Type: hybrid Over 50,000 customers globally trust our end-to-end, cloud-driven networking solutions. They rely…

ai analytics api automation aws +40 skills
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Spirent Communications
3 weeks ago

Senior Software Engineer

Open 20d North AmericaFull-timeSenior H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Designs and implements a Linux abstraction layer (C/C++) to decouple core software logic from volatile /sys and /etc interfaces, ensuring resilience across OS/kernel upgrades while collaborating with teams on testing, packaging, and future-proofing strategies.

ai ansible api automation bash +12 skills
107 120 – 170 000 $
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Tata Capital
3 weeks ago

Sales Manager - NCV Finance - Other OEM - Motor Finance - Sales - Vashi - Ambience Court - (M1-M3)

Open 43d APAC
India

Key Deliverables: Lead generation Ensure necessary leads are generated through BDMs and channel partners/open market Customer relationship management Develop and maintain relationship with existing and potential…

lead-generation performance-management tcl
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onsemi
3 weeks ago

Senior Design Verification Engineer

Open 20d APACSenior
India

Leads digital IC verification for mixed-signal IP (DACs, ADCs, PLLs) in automotive/industrial/medical products, designing SystemVerilog/UVM environments, debugging RTL, and improving verification methodologies.

embedded-software python signal-processing tcl verilog
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Normal Computing
3 weeks ago

Hardware Engineer, RTL/PD

Europe, North America, UKFull-time

Hardware Engineer, Physical Design Department: Engineering Location: New York City, London, Zurich, Silicon Valley, Copenhagen Compensation: $200K – $400K • Offers Equity Employment Type: FullTime About Normal…

accessibility ai hpc python tcl
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Astera Labs
3 weeks ago

Manager, Physical Design Engineer

Open 70d On-siteNorth America H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Canada

Manages a team of physical design engineers in Toronto to implement high-speed connectivity ASICs for AI infrastructure, using advanced EDA tools and TSMC nodes.

agentic-ai ai automation cad ethernet +4 skills
180 000 – 220 000 CAD
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Astera Labs
3 weeks ago

Senior/ Staff Physical Design Engineer

Open 70d MENAStaff H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Israel

Designs and implements high-performance semiconductor chips for AI infrastructure, focusing on physical design flows, signoff, and automation in advanced process nodes.

ai automation ethernet pcie python +1 skills
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Astera Labs
3 weeks ago

Principal Physical Design Engineer, STA

Open 70d On-siteNorth AmericaPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Principal Physical Design Engineer (STA) at Astera Labs designs and optimizes timing for high-performance connectivity ASICs used in AI infrastructure, leveraging advanced EDA tools and TSMC 7nm processes.

ai automation cloud ethernet networking +6 skills
209 000 – 250 000 $
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Astera Labs
3 weeks ago

Senior/ Staff Front-End CAD Engineer

Open 70d MENAStaff H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Israel

Designs and automates chip design flows for semiconductor connectivity solutions, using Python, Tcl, and EDA tools to optimize RTL generation and hardware development.

ai automation backbone cad ethernet +8 skills
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Astera Labs
3 weeks ago

Technical Lead Physical Design Engineer

Open 70d On-siteNorth AmericaLead H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Leads the physical design of high-performance connectivity ASICs for AI infrastructure, using advanced EDA tools and methodologies for 7nm or smaller process nodes.

ai cloud ethernet networking pcie +4 skills
135 000 – 195 000 $
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Astera Labs
3 weeks ago

Staff/ Principal Physical Design STA Engineer

Open 70d MENAPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Israel

Senior/Staff STA Engineer at Astera Labs in Israel designs and signs off timing for high-performance AI connectivity chips, using EDA tools and SDC constraints to meet aggressive data-center targets.

ai automation ethernet pcie perl +2 skills
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Astera Labs
3 weeks ago

Staff Physical Design Engineer - SoC EMIR Engineer

Open 70d MENAStaff H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Israel

Designs power integrity and electromigration checks for AI-focused semiconductor chips, using tools like Ansys RedHawk and Cadence Voltus to ensure reliability in advanced FinFET nodes.

ai ansys cloud ethernet pcie +1 skills
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Astera Labs
3 weeks ago

Staff/ Principal Design Verification Engineer

Open 70d MENAPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Israel

Designs and implements verification environments for high-performance semiconductor chips in AI infrastructure, using SystemVerilog/UVM to validate digital blocks and subsystems.

ai ethernet networking pcie python +2 skills
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Astera Labs
3 weeks ago

Staff/ Principal Physical Design CAD Engineer

Open 70d MENAPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Israel

Designs and automates semiconductor chip implementation flows, focusing on parasitic extraction and GenAI-driven methodologies to optimize high-speed AI connectivity chips from RTL to GDSII.

agentic-ai ai automation cad ci-cd +9 skills
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Astera Labs
3 weeks ago

Staff/ Principal Physical Design Engineer - SoC EMIR Expert

Open 70d MENAPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Israel

Designs power integrity and electromigration solutions for high-performance AI chips, ensuring voltage stability and reliability in advanced semiconductor nodes.

ai ansys cloud ethernet pcie +1 skills
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Astera Labs
3 weeks ago

Director, Physical Design

Open 63d APAC H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
India

Leads a team in Hyderabad to design and implement high-speed connectivity ASICs for AI infrastructure, using advanced EDA tools and flows for full-chip physical design and tapeout.

ai automation cad cloud ethernet +6 skills
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Astera Labs
3 weeks ago

Principal Physical Design Engineer, Methodology

Open 29d On-siteNorth AmericaPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Principal Physical Design Engineer defines and maintains reusable RTL-to-GDSII flows and automation for SoC tapeouts, integrating Cadence and Synopsys tools to optimize PPA and schedule predictability.

agentic-ai ai automation cad ci-cd +5 skills
185 000 – 240 000 $
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Cadence Design Systems
3 weeks ago

Lead Software Engineer

APACFull-timeLead
China

Lead Software Engineer - Liberate Location: SHANGHAI Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The candidates…

cpp linux tcl unix verilog +1 skills
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Cadence Design Systems
3 weeks ago

Lead Software Engineer

LATAMFull-timeLead
Brazil

Lead Software Engineer: Jasper R&D Location: BELO HORIZONTE Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence…

cloud cpp oop python tcl +4 skills
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Cadence Design Systems
3 weeks ago

Principal Design Engineer

APACFull-timePrincipal
China

Sr Principal Design Engineer Location: SHANGHAI Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Responsibilities:…

bash ethernet fpga pcie perl +3 skills
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