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Sr Mgr/Dep Director ASIC Digital Design IP ENGINEERING
Leads a team to design and tape out next-gen processor and SoC IP, guiding RTL development, verification, and PPA optimization for high-performance, low-power ASICs.
FPGA Engineer Engineer (eInfochips)
Designs and implements FPGA logic using Verilog/SystemVerilog, PCIe, AXI/APB interfaces, and front-end verification tools for high-speed hardware projects.
Senior Software Engineer, Hardware Tools and Methodology Development
Develops C++ tools and automated workflows for RTL generation and ASIC design at NVIDIA, improving Verilog RTL quality and connectivity algorithms for GPU and AI hardware.
Amazon Design for Test Engineer
Design for Test (DFT) Engineer at Amazon’s Annapurna Labs, building and verifying custom silicon for AWS. Uses Verilog, SystemVerilog, UVM, and scan/debug flows to ensure chip reliability and yield.
Amazon Software Development Engineer, CPLD/FPGA
Develops and maintains programmable logic (CPLD/FPGA) for AWS server designs, using Verilog/VHDL and embedded C/C++ to optimize cloud infrastructure hardware.
Amazon Chip Design Integration Lead
Lead the end-to-end integration of high-performance networking SoCs for AWS Nitro, defining IP blocks, resolving CDC/RDC issues, and driving synthesis/timing closure with Verilog/SystemVerilog and scripting.
Amazon Senior Software Development Engineer, FPGA
Senior engineer designing and implementing FPGA-based hardware and firmware for AWS cloud servers, leading architecture, verification, and team mentorship.
Staff Engineer, Digital Design
Lead RTL design for MCU SoCs, defining micro-architecture and owning IPs to meet PPA targets while mentoring junior engineers and improving design flows.
Electrical Design Engineer
Senior Staff Electrical Design Engineer Location: Palm Bay, Florida, us Job Description The Rad Hard Precision Design Group is seeking a senior level Analog IC designer to join the team in either the Research Triangle…
Senior Staff Electrical Design Engineer
Senior Staff Electrical Design Engineer Location: Morrisville, NC, us Job Description The Rad Hard Precision Design Group is seeking a senior level Analog IC designer to join the team in either the Research Triangle…
Principal Design Verification Engineer
Leads verification strategy for next-gen semiconductor interconnect products, building UVM/SystemVerilog testbenches and driving silicon success for high-speed digital designs.
HPC SoC Timing Design Engineer/Leader
HPC SoC Timing Design Engineer/Leader Team: Software Engineer Location: Japan Commitment: Full- Time Workplace Type: onsite We're hiring an HPC SoC Timing Design Engineer/Leader for a global semiconductor company…
Senior FPGA Engineer
Designs and debugs FPGA firmware for high-speed RF/wireless systems, including DSP, JESD204C, and 100G Ethernet, using VHDL/Verilog and Python/C/C++.
Hardware FPGA/ASIC Engineer
Designs and validates high-performance digital circuits (FPGA/ASIC) and embedded software for aerospace/defense projects, using VHDL/Verilog and tools like Altium/Cadence.
FPGA Specialist, Aeronautics
Design and validate complex FPGA/SOC systems for critical aeronautics applications using VHDL/Verilog, ensuring compliance with DO-254 and collaborating with hardware/software teams.
FPGA Engineer
Design and validate complex FPGA/SOC designs for critical aerospace systems using VHDL/Verilog and industry tools, ensuring compliance with safety standards.
AI/ML Camera Lead Engineer
Lead the design of camera and image-processing ASIC IP blocks using RTL, synthesis, and PPA analysis, while driving GenAI tools for hardware workflows and agentic AI solutions.
CPU Micro-architect/RTL Designer
Designs and implements CPU micro-architectures and RTL for high-performance, low-power chips, collaborating with architects and verification teams.
Physical Design Engineer
Designs and implements ASIC physical layouts for DSP cores used in mobile, compute, and AI products, handling floorplanning through tapeout.
Infrastructure Design Verification Senior Engineer
Designs and verifies high-speed interconnect protocols (PCIe, CXL, AXI) using UVM and SystemVerilog to ensure ASIC/subsystem correctness before tape-out.