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Exploitation Analyst Instructor-Senior
Senior instructor designs and delivers advanced cyber training, building realistic VMware labs and courseware to teach exploitation analysis to government analysts.
Akamai Security Consultant (Remote)
Advise high-profile financial customers on web security, architecture, and AI platforms, designing solutions to optimize performance and security posture.
Java Developer
Build and maintain Java-based sanctions and AML applications using Spring, REST, and SQL; collaborate with global teams in an agile, DevOps-driven environment.
ASIC/FPGA Verification engineers
Design and run verification environments for ASIC/FPGA chips using SystemVerilog/UVM, then execute test cases to ensure hardware correctness.
RTL Design Engineer, Silicon
Designs and codes RTL for custom silicon subsystems using Verilog/VHDL, integrates IP, and runs simulations and checks to deliver high-performance hardware for Google’s products.
Web Developer (Perl)
Build and maintain company websites and web services using Perl, JavaScript, SQL, and UNIX tools for a cybersecurity product company.
Design Verification Engineer, Networking, Google Cloud
Verify custom silicon designs for Google Cloud, building constrained-random test environments in SystemVerilog/UVM to uncover bugs and ensure tape-out readiness.
Experienced Engineer - FPGA CAD
Build and maintain FPGA CAD tools and automation flows in Python/Tcl to speed up synthesis, place & route, and verification for Ericsson’s radio/RAN compute products.
Director, Embedded Memory
Lead a team to design and deliver embedded memory compilers (SRAM, ROM, register files, DPRAM) for SoC integration, setting PPA targets, customer requirements, and silicon validation.
PostgreSQL Database Administrator
Senior PostgreSQL DBA responsible for designing, securing, and optimizing production PostgreSQL databases, ensuring high availability and performance for a government client.
Нагрузочный тестировщик
Senior performance engineer designs and runs load tests for distributed systems using Java/Python, JMeter, and Kubernetes, then analyzes results in Grafana/InfluxDB to find bottlenecks.
RHEL Systems Administrator (CAMEO)
Administers Red Hat Enterprise Linux servers for a federal government system, ensuring uptime, security, and user access in a cloud environment while supporting virtual desktops and scripting automation.
Digital Design Engineer
Designs and debugs RTL for AMD’s Infinity Data Fabric, optimizing for power, timing, and area while collaborating with global teams.
Senior QA engineer (Networking, Linux) for system team (IRC299967)
Senior QA engineer tests cloud-native cable access software (CableOS) on Linux, validating networking protocols, performance, and integration across microservices and hardware.
RTL Design Engineer – FPGA High-Speed Connectivity IP
Design and validate high-performance RTL IPs for FPGA high-speed connectivity subsystems using VHDL/Verilog and AMD/Xilinx toolchains.
DevOps AI Agent Engineer
Build and validate AI agents and DevOps workflows to automate hardware validation, debug SOC bring-up issues, and optimize AMD’s product delivery pipeline.
PLL Design Engineer
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And…
Mask Layout Designer
Designs and verifies advanced semiconductor mask layouts for high-performance processors, collaborating with circuit teams to ensure tape-out readiness using industry-standard tools.
Staff Silicon Design Engineer
Designs and executes SoC verification for AMD’s next-gen ASIC and FPGA chips, writing testbenches in SystemVerilog/UVM and debugging failures to ensure bug-free silicon.