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Early Career Analog Mixed-Signal Design Verification Engineer (m/f/d)
Verify next-gen power-management ICs for Apple’s PMU team, writing test plans and environments in SystemVerilog/Verilog-AMS to ensure high-quality silicon tape-outs.
Physical Design Engineer, Block Level, Subsystem Implementation
Physical Design Engineer - Block Level, Subsystem Implementation Department: ASIC Location: Austin Compensation: $200K – $300K • Plus Significant Equity Employment Type: FullTime About Etched Etched is building…
Hardware Verification Engineer / Инженер верификатор
Verifies digital hardware blocks using SystemVerilog/UVM, builds test environments, and automates verification with Python/TCL for SoC projects.
IC Design Exploration Intern
An intern in AMD’s Singapore design center works on cutting-edge IC design tasks like analog/digital design, verification, or post-silicon validation using EDA tools such as Cadence and Synopsys, contributing to high-speed SerDes and AI-related chips.
Hardware Engineer, Physical Design
Hardware Engineer specializing in RTL/PD, optimizing designs from microarchitecture to tapeout for AI-native ASICs at Normal Computing, a deep-tech semiconductor startup.
Senior ASIC Backend Engineer
Senior Engineer - Physical Design Location: Bangalore,Karnataka,India Department: 76 Product Development Work Location: onsite Grow with us About this Opportunity Join Ericsson's cutting-edge journey to shape the…
Experienced Analog Mixed-Signal Design Verification Engineer (m/f/d)
Design verification engineer at Apple’s Nabern office, verifying next-gen power-management ICs using mixed-signal verification flows, hardware description languages, and analog behavioral models to ensure high-quality silicon tape-outs.
SOC Physical Design Engineer (Contract / up to $7K)
Designs and optimizes physical layouts for System-on-Chip (SoC) components, focusing on floor-planning, place-and-route, and power/timing optimization to prepare designs for manufacturing.
Staff Engineer- RTL Design
Designs and implements high-performance memory compilers and RTL blocks for custom SoCs, collaborating with architecture, verification, and physical design teams to deliver silicon-ready IP.
Senior Network Engineer (Government Sector)_Contract
Senior Network Engineer designs and implements network solutions for government ATM projects, leading small teams and ensuring compliance with security standards using Cisco and Linux technologies.
Technical Staff Engineer-Design
Designs low-power wireless System-on-Chip solutions, writing RTL code and guiding the SoC through synthesis, timing analysis, and tape-out while collaborating with global teams.
DFT Design Engineer
Designs and validates chip-level test structures (JTAG, MBIST, scan/ATPG) to ensure silicon quality and manufacturability, collaborating with design and verification teams.
Hardware Principal Engineer
Principal ECAD Library Engineer at Dell designing and maintaining Cadence Allegro/OrCAD symbols, footprints, and standards to ensure high-quality hardware development for laptops, servers, and peripherals.
ASIC Design Engineer
Designs and implements ASIC/SoC RTL (Verilog/SystemVerilog) for high-performance SSD controllers, collaborating with verification, validation, and firmware teams to deliver next-gen enterprise and AI data center storage solutions.
TPU SoC Design Engineer, Cloud
Designs and verifies custom silicon for Google's TPU AI accelerators, focusing on SoC-level RTL, architecture, and integration within AI/ML systems.
Senior ASIC Package Design Automation and AI Engineer
Designs and deploys AI-driven automation workflows to optimize semiconductor package, bridge, and interposer design processes using EDA tools and AI/ML techniques.