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DevOps AI Agent Engineer
Build and validate AI agents and DevOps workflows to automate hardware validation, debug SOC bring-up issues, and optimize AMD’s product delivery pipeline.
PLL Design Engineer
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And…
Mask Layout Designer
Designs and verifies advanced semiconductor mask layouts for high-performance processors, collaborating with circuit teams to ensure tape-out readiness using industry-standard tools.
Staff Silicon Design Engineer
Designs and executes SoC verification for AMD’s next-gen ASIC and FPGA chips, writing testbenches in SystemVerilog/UVM and debugging failures to ensure bug-free silicon.
Silicon Design Engineer
Lead verification of AMD’s IOHUB subsystem, defining test plans and collaborating with global teams to ensure high-performance interconnect IP meets design specs.
Staff Silicon Design Verification Engineer, PCIe
Verify next-gen PCIe controller designs for AMD’s SoCs, using SystemVerilog/UVM testbenches and low-power techniques to ensure performance and power targets for AI, gaming, and server chips.
Staff Design Verification Engineer
Design verification engineer at AMD, building and automating tests for next-gen network processors and SmartNICs using UVM, SystemVerilog, and AI-assisted workflows.
Senior Systems Design Engineer
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…
ASIC Design Verification Engineer
Design and verify next-gen ASICs using SystemVerilog and UVM, collaborating with architects and engineers to ensure first-pass silicon success.
Design Verification Engineer
Design Verification Engineer at AMD builds and runs testbenches in SystemVerilog/UVM to validate DDR5/LPDDR5 memory interfaces and DFI protocols for server products.
Principal Staff Silicon Design Engineer, DDR Verification
Lead verification of DDR5/LPDDR5 memory interfaces for server products using SystemVerilog, UVM, and formal methods; mentor engineers and collaborate with hardware, firmware, and software teams.
Staff Design Verification Engineer
Design Verification Engineer at AMD building and running testbenches for DDR5/LPDDR5 memory interfaces using SystemVerilog, UVM, and C/C++ to validate server memory products.
Physical Design Engineer
Designs and implements physical layouts for high-performance chip IP, owning floorplanning through GDS tape-out on advanced nodes (28nm or below).
Senior DevOps Engineer
Senior DevOps Engineer automates deployments, monitors systems, and maintains cloud infrastructure (AWS/GCP) using Docker, Kubernetes, CI/CD, and scripting.
Hardware Security Engineer
Design and develop secure hardware IPs like post-quantum crypto accelerators and random number generators using Verilog/SystemVerilog, collaborating with architects and software teams to meet security and quality standards.
Software Development Engineer
Develops automation tools and flows for front-end chip design verification, synthesis, and package generation using SystemVerilog, Python, and EDA tools.
Senior Staff Engineer, Physical Design
Leads block- and subsystem-level physical design closure for complex SoCs, focusing on timing, congestion, power integrity, and clocking while collaborating with SoC teams.
Integration Engineering - Software Engineer
Builds and maintains large-scale Java-based integration platforms for Apple’s global operations, using middleware like Apache Camel and NoSQL databases to connect systems at massive scale.
Advanced Embedded Software Engineer, Computer Enhanced
Design, code, and test embedded C software for automotive gateway ECUs, using AUTOSAR, CAN/Ethernet, and diagnostic protocols while following ASPICE and Agile processes.
Systems Administrator - Sr. Consultant
Senior systems administrator at Visa providing 24/7 support for global payment networks, automating ops with Python and GenAI, and hardening Linux servers to meet PCI-DSS and ITIL standards.