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Leads a team to verify next-generation AI infrastructure SoCs using UVM, formal methods, and emulation, ensuring first-pass silicon success for complex designs in compute and networking.
Leads post-silicon engineering programs for AI connectivity ASICs, coordinating silicon bring-up, validation, and manufacturing release across cross-functional teams.
Leads cross-functional ASIC development programs from planning through tapeout, coordinating RTL design, verification, physical design, and external partners to deliver custom silicon for AI infrastructure.
Principal Optical Test Engineer at Astera Labs designing and executing test strategies for next-gen Co-Packaged Optics (CPO) solutions, integrating silicon photonics and high-speed optical modules for AI and hyperscale data centers.
Leads validation and characterization of advanced photonic integrated circuits (PICs) integrated with electronic ICs for high-speed data center and AI applications, using optical and electrical testing tools.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
Designs high-performance digital IP for AI connectivity chips, focusing on RTL, synthesis, and integration of processor and peripheral IPs at advanced semiconductor nodes.
Leads SoC design for high-performance connectivity chips, owning RTL, synthesis, timing closure, and pre/post-silicon debug at advanced process nodes using Synopsys/Cadence tools.
Leads timing closure and sign-off for high-speed connectivity ASICs at Astera Labs, using advanced STA tools and methodologies for 7nm+ SoCs in AI infrastructure.
Leads a team to design test strategies for high-speed PCIe switch chips using advanced 2.5D/3D packaging, ensuring manufacturability and quality for AI infrastructure components.
Lead embedded firmware development for analog and Ethernet connectivity devices, writing C/C++ code for calibration, link management, and hardware bring-up in a fast-moving AI infrastructure startup.
Designs and implements high-performance digital ASIC blocks for AI infrastructure connectivity chips, from RTL to backend, using Verilog/SystemVerilog and EDA tools.
The Firmware Engineer Tech Lead will architect and develop firmware for SoC and system products, focusing on connectivity solutions for AI infrastructure. The role involves implementing key product features, collaborating with hardware teams, and engaging directly with customers.
Senior Capacity Planning Analyst at Astera Labs in San Jose builds and maintains data-driven capacity models for semiconductor supply chains, using tools like Power BI, Databricks, and Oracle to forecast production and resolve bottlenecks.
Senior Sourcing Specialist in Taipei manages procurement, supplier relations, and purchasing for Astera Labs' Asia operations, including lab equipment, facilities, and office needs across multiple cities.
Lead a team to design, build, and maintain enterprise and cloud networks using routing, switching, firewalls, and cloud connectivity for a company delivering AI infrastructure solutions.
Principal Physical Design Engineer defines and maintains reusable RTL-to-GDSII flows and automation for SoC tapeouts, integrating Cadence and Synopsys tools to optimize PPA and schedule predictability.
Leads power integrity analysis for AI connectivity ASICs, ensuring stable power delivery and reliability through IR drop and electromigration sign-off from floorplan to tapeout.
Leads a team to design and tape out advanced multi-die switching chips for AI infrastructure using UCIe, UALink, and PCIe Gen 6/7 in 7nm or smaller process nodes.
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