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Analog Designer
Designs and verifies custom IC layouts for analog and digital circuits using Cadence Virtuoso and Mentor Calibre, including PLLs, DACs, and high-speed signaling blocks.
Layout Designer
Designs and verifies semiconductor device layouts using EDA tools like Cadence Virtuoso and Synopsys, ensuring design rules and physical verification standards are met.
Senior Engineer, CMOS & Metallization Test Structure Design and Layout
Designs and lays out CMOS and metallization test structures for semiconductor R&D, using EDA tools like Cadence Virtuoso and Calibre to enable DRAM/NAND process development and reliability analysis.
Senior Layout Designer
Designs and verifies semiconductor layouts using EDA tools like Cadence Virtuoso and Synopsys, collaborating with global teams to optimize chip designs and improve efficiency.
Principal Memory Design Engineer, HBM
Lead DRAM circuit design for high-bandwidth memory, optimizing power, performance, and reliability using Cadence Virtuoso, HSPICE, and Verilog.
Senior Engineer, Standard Cell Design
Design and optimize standard cells for DRAM memory, automate characterization flows, and collaborate on AI-assisted tools to improve timing, power, and performance models.
Semiconductor Design Engineer
Design and optimize CMOS memory circuits for DRAM and emerging memory tech, using SPICE/Verilog tools and collaborating with global teams to deliver high-quality semiconductor products.
Mixed Signal IC Layout Design Engineer - Contractor
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify…
Senior SRAM Circuit Design Engineer (Remote)
Senior SRAM Circuit Design Engineer Location: US, CA, Santa Clara, US, CA, Remote Time Type: Full time Job Description NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than…
Sr Staff Mask Design Engineer
We are looking for an experienced Sr Staff Mask Design Engineer to join a highly skilled layout organization working on Analog and Mixed‑Signal ICs for Automotive applications . The role involves defining, developing,…
Engineer - Design Enablement Design Manual Engineer
Develops and validates semiconductor design rules for GlobalFoundries’ manufacturing processes, ensuring manufacturability and technological competitiveness through data-driven experiments and silicon validation across US and Singapore sites.
Sr. Principal Design Engineer
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. 1. Role Overview & Objective We are looking for a motivated SRAM Circuit Design Engineer to join our…
Research Assistant/Engineer (Integrated Circuits Design)
Designs low-power, high-performance integrated circuits for analog-to-digital converters using EDA tools like Cadence Virtuoso and Synopsys, and collaborates with industry partners on tape-out and testing.
Senior Mixed Signal Design Engineer
Design high-speed analog/mixed-signal circuits for next-gen NVLINK using Spectre/HSpice and Cadence Virtuoso, from schematic to silicon bring-up.
Analog Designer (1 year contract)
Designs and verifies analog and digital IC layouts (PLL, DAC, VCO, etc.) using Cadence Virtuoso and Mentor Calibre, from cell-level blocks to full chip integration.
Silicon Design Engineer
Designs and verifies electrostatic-discharge protection circuits for advanced ASIC/FPGA chips using SPICE simulations, layout reviews, and foundry PDKs.
RF Design Engineer
Designs high-frequency RF ICs (30 GHz+) for 5G/6G, radar, and sensors using Cadence tools and advanced RF SOI processes.
Early Career - AI for Analog Design Engineer
Build AI models and agents to accelerate analog circuit design, sizing, and layout for Texas Instruments' IC teams using MLPs, RNNs, CNNs, GNNs, and transformers.
Hardware & Silicon Validation Engineer
Design and validate ultra-dense SRAM memory compilers for chip companies and big tech, using Cadence Virtuoso, Spectre X, Python, and Linux.
Memory Circuit Design
Designs and optimizes high-performance, low-power memory circuits (SRAM/DRAM) using transistor-level design and SPICE simulations for advanced semiconductor nodes.