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Design Verification Engineer, Cloud Silicon
Design Verification Engineer who builds and runs tests to ensure Google’s TPU silicon works flawlessly for AI/ML workloads, using SystemVerilog, UVM, and coverage-driven flows.
Principal Design Team Leader
Leads a hardware design team developing 5G baseband IP for satellite-based base stations, focusing on power efficiency and delivery of Layer 1 IP using RTL, FPGA, and ASIC techniques.
Senior Hardware Design Engineer
Designs and implements FPGA/ASIC hardware for satellite-based 5G base stations, focusing on signal processing and power efficiency using Verilog/SystemVerilog and EDA tools.
Design Engineer
Design Engineer at AccelerComm develops advanced IP, system, and board solutions for 5G wireless communications, using SystemVerilog, EDA tools, and hardware optimization techniques.
FPGA Developer - Kitchener, Ontario, Canada
Designs and optimizes high-performance FPGA hardware for financial trading systems, using Verilog/SystemVerilog and modern FPGA toolchains, with a focus on low-latency interfaces like 100GbE and PCIe.
Integrated Circuit Design Verification Engineer
Design and verify integrated circuits for AR display systems, building UVM-based testbenches and using Siemens Questa for simulation and debug.
Principal IC Digital Design - SoC Design/Micro-architecture
Principal IC Digital Design Engineer leads SoC micro-architecture, RTL development, and HW/SW co-design for advanced semiconductor solutions used in AI, cloud, and telecom.
Senior FPGA Designer
Designs and implements FPGA logic for optical telecommunication products, collaborating with hardware and firmware teams to validate and optimize high-speed data transmission systems using Verilog/SystemVerilog and AMD/Xilinx or Altera tools.
Senior/ IC Design Engineer (Design Verification)
Design verification engineer building and running SystemVerilog/UVM testbenches to validate ASIC/SoC designs, using AI-assisted tools to improve coverage and debug efficiency.
Sr/ IC Design Engineer (Design Verification)
Design verification engineer building UVM-SV testbenches and coverage plans to validate complex ICs and SoCs before tape-out.
ASIC Engineer || RTL Design, Verilog, System Verilog || CDC, Lint || Exp - 4 to 7 years
Designs and validates high-performance ASIC chips for Cisco's networking solutions using Verilog/SystemVerilog, CDC, lint, and formal verification, from architecture through tape-out and lab validation.
Senior Software Engineer, SOC Design Methodology
Senior engineer building automation tools and methodologies to accelerate NVIDIA’s ASIC and SoC chip design flows, working with EDA vendors and RTL teams.
Principal Modem PHY IP Design Verification Engineer - Terawave
Principal engineer verifying advanced modem PHY IP for Blue Origin’s Terawave satellite network, ensuring high-speed wireless ASIC designs meet performance and integration requirements.
Manager, SOC Verification
Sr. Manager - SOC Verification Location: India - Bangalore Time Type: Full time Job Description Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on…
Principal Design Engineer
Principal Design Engineer Location: SHANGHAI Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Key Responsibilities…
Design Verification Engineer for DFT
Design Verification Engineer in Cisco’s DFT team validates testability features for advanced networking and AI silicon using SystemVerilog/UVM, collaborating with cross-functional teams to ensure chip reliability and performance.
Logic Design Engineer
Designs and optimizes logic circuits for next-generation wireless connectivity chips using SystemVerilog and AI-assisted tools, ensuring power, performance, and timing requirements are met.