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Design Verification Engineer for DFT
Design Verification Engineer in Cisco’s DFT team validates testability features for advanced networking and AI silicon using SystemVerilog/UVM, collaborating with cross-functional teams to ensure chip reliability and performance.
Logic Design Engineer
Designs and optimizes logic circuits for next-generation wireless connectivity chips using SystemVerilog and AI-assisted tools, ensuring power, performance, and timing requirements are met.
Hardware Engineer Intern
Hardware Engineer Intern - Summer 2027 Location: Chicago, United States Department: Development (Group) Our 10-week internship is your chance to experience life as a Hardware Engineer at IMC. You’ll have the support…
Hardware Engineer
Hardware Engineer Location: Chicago, United States Department: Development (Group) IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next generation of custom ASICs that power our…
Graduate Hardware Engineer
Graduate Hardware Engineer Location: Chicago, United States Department: Development (Group) Having the best technology drives our business. As a Hardware Engineer at IMC, you are responsible for spotting new…
FPGA Verification Engineer
FPGA Verification Engineer Level 3/4 - Linthicum Location: United States-Maryland-Linthicum Time Type: Full time Job Description RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR…
FPGA Verification Engineer
FPGA Verification Engineer Level 5 - Linthicum Location: United States-Maryland-Linthicum Time Type: Full time Job Description RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR START:…
Senior ASIC Design Engineer
Senior Engineer - ASIC Design Location: Bangalore,Karnataka,India Department: 76 Product Development Work Location: onsite Grow With Us: About this opportunity: We are starting a new Silicon R&D center in…
Design Verification Engineer
Design Verification Engineer at indie builds and executes verification strategies for next-gen automotive camera processors using SystemVerilog, UVM, and C/C++.
Design Verification Engineer, Coherent Interconnect
Designs and verifies high-performance coherent interconnect IP for Samsung’s SoCs, using SystemVerilog/UVM and ARM protocols to ensure low-latency, power-efficient solutions for next-gen mobile devices.
Design Verification Engineer (Silicon Engineering)
Designs and verifies next-generation ASICs for SpaceX’s Starlink network, using SystemVerilog, UVM, and Python to ensure reliable satellite and ground infrastructure connectivity.
Design Verification Engineer (Silicon Engineering)
Design Verification Engineer at SpaceX developing and testing next-generation ASICs for Starlink's satellite and ground infrastructure using SystemVerilog, UVM, and Python.
FPGA/ASIC Design Engineer (Silicon Engineering)
Designs and optimizes FPGAs and ASICs for SpaceX's Starlink network, using Verilog/SystemVerilog and collaborating with cross-functional teams to enhance satellite and ground infrastructure performance.
RTL Design Engineer (Silicon Engineering)
Designs and implements FPGAs and ASICs for SpaceX's Starlink network using Verilog/SystemVerilog, collaborating across teams to enhance satellite and ground infrastructure connectivity.
AI Silicon, Junior Digital Design Engineer
Junior Member of Technical Staff - AI Silicon Digital Design Engineer About Unconventional Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental…
AI Silicon, Design Verification
About Unconventional: Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental consumer behaviors. This revolution has created an unprecedented…
Design Verification Engineer (Sunnyvale)
We are looking for a Design Verification Engineer to support SoC-level verification of advanced high-speed and security IP. This role involves close collaboration with design and architecture teams to verify complex…
Group Director, Design Engineering - Front End
Leads a team of RTL design engineers to architect and develop semiconductor IP and subsystems, focusing on front-end design, verification, and PPA optimization using Verilog/SystemVerilog/VHDL.