Tech jobs
Job listings
SoC/FPGA Engineer
Designs and verifies ASICs and FPGAs for high-speed optical transmission systems, implementing signal processing algorithms and collaborating with global teams to optimize power and performance.
Senior Engineer I Design
Design-for-Test engineer responsible for inserting boundary scan, memory BIST, and scan logic into complex SoCs, running ATPG, and debugging silicon bring-up on ATE.
DRAM Design Working Student in Munich (m/f/d)
Working student role in DRAM design, assisting engineers with IC schematics, simulations, and verification for high-performance memory solutions in Munich.
Full-Chip Senior Principal Physical Design Engineer
Lead the physical design and implementation of high-performance processor chips from RTL to GDS in advanced nodes (5nm–2nm), managing global teams and sign-offs for timing, power, and DFM.
Full-Chip Principal Physical Design Engineer
Lead the physical design and methodology for next-gen high-performance processor chips, managing RTL-to-GDS flows, timing, power, and sign-offs in advanced nodes (5nm–2nm) for server, 5G/6G, and networking applications.
IP Physical Design Engineer
Designs and optimizes high-performance processor chips from RTL to GDSII, leading physical design flows and automation for server, 5G/6G, and networking applications.
Software Engineer II: Jasper R&D
Builds and tests Jasper, a formal-verification tool for clock-domain-crossing issues in chip design, using C++ and Unix workflows.
Lead Software Engineer: Jasper R&D
Lead a team enhancing Jasper, a formal verification tool for clock domain crossing in hardware design, using C++ and Unix in a fast-paced R&D environment.
Senior Staff Engineer, Physical Design (Floorplanning)
Senior engineer leading physical design and floorplanning for high-performance GPUs and SoCs at advanced technology nodes, optimizing power, performance, and area while mentoring peers and driving EDA/tool innovation.
Senior FPGA and Firmware Design Engineer
Design and implement FPGA logic in VHDL/Verilog, write embedded Linux firmware with Yocto/PetaLinux, and integrate hardware/software for aerospace and defense systems.
FPGA Prototype 엔지니어 (SoC/IP Prototyping)
Design and prototype next-gen AI hardware using FPGAs, focusing on SoC emulation, high-speed interfaces like PCIe/LPDDR, and bring-up for analog compute-in-memory chips.
DFT Design Engineer
Designs and implements automated test and debug features for AMD's complex processor and GPU chips, using scripting and AI/ML tools to improve chip reliability and performance.
ASIC Design Engineer — IP Integration & Implementation
Designs and integrates high-performance, low-power pixel processing ASICs for Apple’s SoCs, collaborating across teams to deliver functional multimedia IP for millions of devices.
Инженер - программист ПЛИС / FPGA Designer
FPGA engineer designs, tests, and integrates Verilog-based image-processing IP cores and high-speed interfaces for embedded systems in an on-site Moscow role.
Software Engineer, Kernel Programming
Develop and optimize low-level AI kernels for FuriosaAI’s Tensor Contract Processor (TCP) architectures, enabling high-performance integration of vision, multimodal, and VLA models.
Senior Firmware Developer
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…
Java Developer
Développeur Java F/H Location: Lyon, Auvergne-Rhône-Alpes, fr Description de l'entreprise Le groupe Coexya, leader du numérique et multi-spécialiste (conseil, intégration & développement), compte plus de 950…
Lead .NET Developer
Lead développeur .NET F/H Location: Lyon, Auvergne-Rhône-Alpes, fr Description de l'entreprise Le groupe Coexya, leader du numérique et multi-spécialiste (conseil, intégration & développement), compte plus de…