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Group Director, Design Engineering - Front End
Leads a team of RTL design engineers to architect and develop semiconductor IP and subsystems, focusing on front-end design, verification, and PPA optimization using Verilog/SystemVerilog/VHDL.
Senior Staff Engineer, Digital IC Design
Designs, verifies, and implements RTL for power management ICs and SoCs, collaborating with architects and verification teams to deliver high-performance semiconductor solutions.
Sr. Manager - SOC Verification
Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment,…
Design Verification Infrastructure Sr. Staff Engineer
Senior engineer builds and maintains a Python-based verification framework for semiconductor design, integrating AI triage while ensuring reproducibility and CI/CD for hardware verification teams.
Senior Digital ASIC Design Engineer
Designs and implements digital ASICs for scientific instruments, focusing on low-power, radiation-aware systems for particle detectors and high-energy physics applications using SystemVerilog/Verilog and EDA tools.
TPU Design Engineer, Silicon
Designs and optimizes custom silicon hardware components for Google's products, focusing on performance, power efficiency, and integration using RTL and Verilog.
Digital Design Engineer
Designs and implements PCI Express IP blocks in Verilog/SystemVerilog for AMD’s server, client, GPU, and semi-custom chips, collaborating across RTL, verification, and post-silicon bring-up.
Senior Flight Software Engineer
Develops and verifies real-time, fault-tolerant flight software for high-power satellites using Rust, C++, and Python, controlling propulsion, attitude, and power systems.
Director, Digital Design & Verification
Leads digital design and verification for semiconductor programs, ensuring silicon success through robust methodologies like UVM, formal verification, and AMS/DMS co-simulation while driving automation and team scalability.
Senior Design Verification CAD Engineer, Silicon, Google Cloud
Designs and verifies custom silicon for Google's TPU AI hardware, leading teams to ensure flawless chip performance in AI/ML systems.
Senior FPGA Engineer
Senior FPGA Engineer designs ultra-low-latency trading systems using HDLs like SystemVerilog/VHDL, Python/C++, and collaborates with quants and traders to optimize performance.
CPU Design Verification Engineer
Designs and verifies custom CPU hardware for Google's consumer products, building verification environments and diagnostic code to ensure performance and functionality.
Staff RTL IP/Component Design Engineer, Google Cloud
Designs and implements complex ASIC/SoC components for Google Cloud using RTL languages, collaborating with cross-functional teams to optimize performance, power, and area.
RTL Design Engineer
Designs and implements digital logic and IP for AI chips or SoCs using Verilog/SystemVerilog, verifies functionality, and integrates IP into larger systems with front-end design flows.
Analog/Mixed-Signal Circuit Design Engineer
Job Title: Analog/Mixed-Signal Circuit Design Engineer Office Location: San Jose, CA Job Type: Full-Time Work Model: Onsite About SK hynix America At SK hynix America, we're at the forefront of semiconductor…
Principal Compute Pathfinding ASIC Design
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into…