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Security Researcher
Research and develop security solutions for 5G/6G and IoT systems, focusing on hardware, protocols, and confidential computations.
Associate Engineer, System Design Engineering ( FPGA Design 2-4 years)
Design and implement high-performance FPGA logic for next-gen NAND Flash storage systems using Xilinx tools and RTL, while collaborating on embedded firmware and system validation.
Design Engineer
The Apple design team is looking for an experienced engineer to develop multiple IPs for Apple SoCs (in Storage, Computer Vision and RISC-V CPU domains). In this Role you will get to handle micro-architecture…
FPGA Software Entwickler für Video / Bildverarbeitung (m/w/d)
Develop FPGA-based video/image processing software using VHDL/Verilog, C/C++, Python, and tools like Vivado/Vitis for embedded systems.
Pld/Fpga-Entwickler Aerospace (m/w/d)
Develop and implement PLD/FPGA solutions for aerospace applications using VHDL or Verilog in a collaborative engineering environment.
RTL IP Design Engineer
Designs and verifies RTL IP blocks for networking solutions, collaborating with architects and physical design teams to ensure first-pass silicon success.
FPGA Emulation Engineer
Build and debug FPGA-based emulation platforms (Synopsys HAPS) to validate complex SoC/ASIC designs and enable early software execution before silicon tape-out.
FPGA Engineer
Design and implement FPGA blocks for high-rate data transport and signal processing in satellite ground stations, using Verilog/SystemVerilog and Python.
DFT Design Engineer
Designs and implements testability features for ASIC/SoC chips, including scan chains, MBIST, and ATPG flows, to ensure manufacturability and high fault coverage.
FPGA Engineer
Design and implement FPGA-based networking and DSP blocks for satellite ground stations, ensuring resilient, high-rate data links for real-time space communications.
Design Verification Engineer
Verify and validate AMD’s next-gen GPU and SOC designs using Verilog/SystemVerilog, UVM, and emulation platforms like Veloce/Zebu to ensure functional correctness and performance.
Staff RTL Design Engineer
Design and implement high-performance RISC-V CPU cores, focusing on microarchitecture, RTL coding, and collaboration with verification and physical implementation teams.
FPGA Engineer
Implement RTL designs on Xilinx FPGAs (Artix-7/Kintex) using Vivado, integrate boards/peripherals, and validate hardware with embedded teams.
Power Management Design Engineer
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive…
Design Verification Engineer
Design Verification Engineer at Cisco in Armenia builds and runs testbenches in SystemVerilog to validate ASIC designs, debug with DVE/Verdi, and script in Tcl/Python/Perl.
RTL Design
Design and implement RTL for next-gen ASICs using Verilog/SystemVerilog, optimizing for performance, power, and area while collaborating with cross-functional teams.
RTL Micro Architect Lead
Lead RTL design and microarchitecture for high-performance SoC subsystems like GPUs and AI accelerators, optimizing for PPA while guiding cross-functional teams.
R&D Engineer IC Design 5
Design and verify high-performance network switch ASICs using SystemVerilog, UVM, and C++, developing complex verification environments and test plans.
Security IP Design Engineer
Designs and verifies hardware security IP for SoCs, including cryptography, key management, and secure boot, using Verilog and SystemVerilog.
Senior SoC Design Verification Engineer
Leads SoC-level verification for a semiconductor company’s edge AI processor (GPNPU), designing testbenches, verifying subsystems (NoC, PCIe/UCIe, DDR), and ensuring hardware-software co-simulation coverage using UVM, Verilog, assembly, and Python.