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Security IP Verification Engineer
Design and verify security IP for SoCs, focusing on cryptography, key management, secure boot, and hardware root of trust using UVM, SystemVerilog, and C.
STAFF ASIC Design Engineer
Designs and implements next-gen SSD controller ASICs, writing RTL, collaborating on verification, and optimizing flows with AI-assisted tools.
Staff Design Verification Engineer – SoC and eFPGA
Design and run verification environments for next-gen eFPGA and SoC IP using UVM, SystemVerilog, and assertions to ensure silicon tape-out quality.
Lead FPGA Engineer
Lead the design, testing, and integration of FPGA firmware for high-performance imaging systems, collaborating with hardware and software teams to meet manufacturing requirements.
Senior NVM Designer
Design and verify non-volatile memory (NVM) circuits for analog AI inference chips, including high-voltage blocks and peripheral logic, using SPICE and Verilog-A.
Hardware Engineer
Design and implement FPGA/ASIC applications using OCaml/Hardcaml, Verilog, and C, focusing on high-level tools for hardware development and testing.
Formal Design Verification Engineer
Designs and verifies hardware components for Microsoft's cloud infrastructure, focusing on formal verification methods and AI-driven solutions to ensure chip reliability and performance.
Senior Product Planning Engineer - Simulation, Security, and Deployment
Lead the roadmap for AMD’s FPGA/SoC simulation tools (UVM, SystemVerilog, HDL), RTL encryption, and deployment workflows, shaping verification methodologies and influencing industry standards.
CPU Design Integration Engineer, Google Cloud
Design and integrate custom silicon for Google Cloud’s AI and hyperscale systems, using Verilog/SystemVerilog and scripting to ensure chip quality and performance.
Staff ASIC Digital Engineer (FPGA Prototyping, Emulation, System-Level Debugging) with 8 to 12 years of experience
Designs and debugs FPGA-based ASIC prototyping platforms, automating bring-up and co-verification between firmware and silicon for Sandisk’s pre-silicon teams.
Senior Staff VLSI Design Engineer (SystemC, Functional Modeling, C++ , Verification)
Leads VLSI design and verification for memory systems, writing C++/SystemC models, testbenches, and debugging firmware issues while mentoring junior engineers.
Staff, VLSI Design Engineering (Verification, NAND, Memory, System Verilog) with 8 to 12 years of experience
Lead verification of complex memory IP and SoCs using SystemVerilog/UVM, formal tools, and automation to ensure silicon success and mentor junior engineers.
Staff VLSI Design Engineering (SOC Verification, System Verilog, UVM)with 8 to 12 years of experience
Lead verification of complex SoC designs using SystemVerilog, UVM, and formal tools; mentor teams and drive silicon success.
Spécialiste FPGA - Aéronautique (F/H)
Design and validate complex FPGA/SOC designs for critical aerospace systems (flight computers, video systems, power management) using VHDL/Verilog and ensuring DO-254 compliance.
Ingénieur Spécialiste Electronique Hardware FPGA / ASIC - F/H
Specialist in FPGA/ASIC hardware design and embedded software, leading technical strategy, mentoring teams, and driving cross-project expertise within an engineering consultancy.
Technical Marketing Engineer – FPGA Design
Technical Marketing Engineer creating training, documentation, and demos for AMD’s Vivado FPGA tool suite, validating features and enabling customers through clear technical communication.