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Lead Software Engineer - Liberate
Lead a team building EDA software in C/C++/TCL on Linux, focusing on semiconductor device simulation and analysis flows like SPICE, timing, and power.
Lead Software Engineer
Lead a team building a distributed, multi-threaded physical synthesis engine for IC design tools, collaborating with global R&D and customer-facing teams using C/C++ on Linux.
Lead Software Engineer
Lead a team building a distributed, multi-threaded physical synthesis engine in C++ for Cadence’s Innovus Implementation System, collaborating with global R&D and supporting customers.
Senior Software Engineer, SOC Design Methodology
Senior engineer building automation tools and methodologies to accelerate NVIDIA’s ASIC and SoC chip design flows, working with EDA vendors and RTL teams.
Physical Design Expert
Physical Design Expert We’re looking for a Physical Design Expert to join the growing Technology Methodology & Execution team, responsible for developing both Technology Methodologies & Flows for all products…
Principal Design Engineer
Principal Design Engineer Location: SHANGHAI Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Key Responsibilities…
Software Engineer (C++)
Software Engineer II (C++) Location: FELDKIRCHEN (Munich), CAMBRIDGE 03 Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.…
Design Engineer
Lead Design Engineer Location: CARY, SAN JOSE Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We offer amazing…
Software Engineer, Synthesis
Software Engineer II, Synthesis Location: SAN JOSE Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Design…
Physical Design Engineer
Physical Design Engineer - Block Level, Subsystem Implementation Department: ASIC Location: San Jose Compensation: $200K – $300K • Plus Significant Equity Employment Type: FullTime About Etched Etched is building…
Physical Design Engineer, Flow & Methodologies
Physical Design Engineer - Flow & Methodologies Department: ASIC Location: San Jose Compensation: $200K – $300K • Plus Significant Equity Employment Type: FullTime About Etched Etched is building hardware for…
Digital Design Engineer
Digital Design Engineer Location: Santa Clara, CA Department: External - Client Requirement Job description : Role Overview We are seeking an ASIC Design Engineer to own digital design, integration, and bring-up for…
FPGA Verification Engineer
FPGA Verification Engineer Level 3/4 - Linthicum Location: United States-Maryland-Linthicum Time Type: Full time Job Description RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR…
FPGA Verification Engineer
FPGA Verification Engineer Level 5 - Linthicum Location: United States-Maryland-Linthicum Time Type: Full time Job Description RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR START:…
Senior ASIC Design Engineer
Senior Engineer - ASIC Design Location: Bangalore,Karnataka,India Department: 76 Product Development Work Location: onsite Grow With Us: About this opportunity: We are starting a new Silicon R&D center in…
Lead Physical design Engineer
Lead the physical design and verification of processor subsystems IP, ensuring tapeout signoff for next-gen chips using EDA tools like Innovus and Fusion Compiler.
Design Verification Engineer
Design Verification Engineer at indie builds and executes verification strategies for next-gen automotive camera processors using SystemVerilog, UVM, and C/C++.
Physical Design Technical Lead, ASIC, TPU
Lead the physical design of next-generation AI silicon (TPUs) for Google, driving RTL-to-GDSII implementation, timing/power closure, and cross-functional collaboration to deliver high-performance custom chips.
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Designs and implements advanced ASIC/SOC chips for SpaceX’s Starlink network, focusing on physical design flows, timing closure, and signoff checks to enable global satellite internet connectivity.