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Lead Design Verification Engineer
Design and implement verification environments for AMD’s Network-on-Chip IPs and SoCs using SystemVerilog/UVM, formal tools, and coverage-driven flows to ensure functional correctness.
Senior Silicon Design Verification Engineer
Design and verify custom silicon for Google’s devices, building UVM testbenches and formal verification flows to ensure ASICs meet performance and reliability targets for AI and image-processing hardware.
Разработчик ПЛИС/FPGA
Designs FPGA/ASIC compute devices using HDL (VHDL/Verilog), writes RTL code, simulates, debugs, and documents high-speed digital circuits.
Principal Engineer- Digital Design
Lead the architecture and RTL design of high-speed switching fabrics for next-gen memory and AI interconnects, guiding teams from spec to silicon bring-up.
Senior/Staff Front-End Engineer (RISC Processor Integration)
Integrate RISC processors (RISC-V/Arm) into SoC platforms, configure subsystems, and collaborate on RTL, firmware, and system bring-up for Bitdeer’s Bitcoin mining and AI cloud hardware.
Principal Engineer- Design Verification
Principal Engineer leads verification strategy for next-gen UA Link Switch SoCs, using UVM/SystemVerilog to ensure first-silicon success for high-speed interconnect and memory subsystems.
PE Logic Design
Principal Design Engineer at Rambus to architect and implement next-gen PCIe IP in System Verilog, prototype on FPGAs, and collaborate with global teams.
Sr. ASIC Design Engineer
Design high-speed networking ASICs from spec to netlist using Verilog/SystemVerilog, work with physical design for timing closure, and collaborate with verification teams.
Hardware Engineer
Design and debug hardware modules, firmware (Verilog), and test software for security screening systems, using tools like Altium, KiCad, and oscilloscopes.
Senior Product Engineer (Electrical Engineering & Embedded Systems)
Designs and troubleshoots embedded systems and PCBs for Illumina’s genomics instruments, guiding products from prototype through manufacturing while ensuring EMC/EMI compliance and cost-efficient production.
Mixed Signal Design Verification Engineer
Verify mixed-signal IPs (e.g., PCIe, USB4/Type-C PHYs) using SystemVerilog/UVM, EDA tools, and scripting to ensure performance and reliability before silicon tape-out.
Senior Front-End Power Engineer
Architects and implements power-analysis techniques for NVIDIA’s next-gen switches, using Verilog, Python, and industry tools to model and reduce chip energy consumption.
Junior Digital Design Engineer
Designs and verifies digital sub-circuits for high-performance micro-controllers using Verilog/SystemVerilog, synthesis, and formal verification, collaborating with analog and software teams.
Principal Firmware Engineer
Principal Firmware Engineer in Luton designing and auto-generating firmware for complex digital systems using MATLAB, Simulink, Verilog, and FPGA tools.
Physical Design Engineer Intern
Internship assisting in the design and physical implementation of digital and mixed-signal ICs for power management and signal functions using ASIC tools like synthesis and P&R flows.
Senior ASIC Design Verification Engineer
Design and verify ASIC blocks and full chips for Cisco’s networking hardware using SystemVerilog/UVM, then bring up silicon and analyze performance.
Principal COE Digital Design Engineer
Principal engineer designing and verifying PCIe/CXL IP subsystems in SystemVerilog for Marvell’s custom SoCs powering hyperscale cloud and AI data centers.
Senior Staff Design Engineer - Memory Subsystem COE
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative…
Logic Designer and FPGA Tech Lead
Lead FPGA architecture and RTL development for real-time medical systems, guiding Verilog/SystemVerilog implementations, timing closure, and hardware bring-up in a regulated healthcare environment.
Ingénieur principal en analogique/ Principal Engineer - Analog Design
Design, simulate, and validate high-speed analog and mixed-signal IP blocks (PLLs, ADCs, DACs, I/O interfaces) for SoC timing products using Cadence tools and Verilog-A.