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Senior Design Verification Engineer, Silicon
Designs and executes verification plans for custom silicon components using SystemVerilog, UVM, and scripting languages to ensure high-performance, low-power hardware for Google's products.
Senior/Staff Design Verification Engineer (SOC)
Design Verification Engineer at Bitdeer in Singapore, responsible for verifying complex digital ASIC designs using UVM, SystemVerilog, and industry tools to ensure functional correctness and silicon quality.
Senior/Staff Front-End Design Engineer (RTL Design - RiscV)
Designs and integrates RISC-V CPU cores with custom extensions for ASIC chips in Bitcoin mining and AI cloud hardware, using Verilog/SystemVerilog and collaborating with cross-functional teams.
Senior/Staff Design Verification Engineer
Design Verification Engineer at Bitdeer in Singapore who builds and runs test environments for ASIC chips and AI cloud hardware using UVM, SystemVerilog, and formal tools to ensure functional correctness before silicon.
Digital Design Engineer, RTL IP, Silicon
Designs and integrates custom silicon IP for Google's hardware products, focusing on RTL design, bus protocols, and SoC milestones.
Principal Engineer, ASIC Design
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into…
Digital Hardware Engineer
Join us in pioneering breakthroughs in healthcare. For everyone. Everywhere. Sustainably. Our inspiring and caring environment forms a global community that celebrates diversity and individuality. We encourage you to…
Digital IC Design Engineer | BCP
Change the world. Love your job. The Battery Charging Products group at Texas Instruments is looking for a candidate that is interested in working in a challenging, fast-paced environment. As a digital design engineer,…
AIML enhanced Design/Verification Methodology Engineer
AIML enhanced Design/Verification Methodology EngineerThis role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global…
Design Verification Manager
Design Verification ManagerThis role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company…
Principal ASIC/FPGA Verification Engineer (Onsite)
Date Posted: 2026-07-21

 Country: United States of America

 Location: US-CA-EL SEGUNDO-E01 ~ 2000 E El Segundo Blvd ~ BLDG E01

 Position Role Type:…
Digital Hardware Engineer
Designs FPGA-based digital hardware and firmware for medical imaging systems, integrating processors and peripherals using VHDL/SystemVerilog and collaborating with cross-functional teams.
Senior Design Verification Engineer
Senior Design Verification EngineerThis role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the…
Senior Design Verification Engineer
Senior Design Verification EngineerThis role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the…
DFT Implementation Engineer
Job Details: Job Description: The Role and Impact As a DFT Design Engineer, you will play a pivotal role in shaping Intel's silicon solutions. Your contributions will directly influence the quality and efficiency…
Digital Hardware Engineer
Join us in pioneering breakthroughs in healthcare. For everyone. Everywhere. Sustainably. Our inspiring and caring environment forms a global community that celebrates diversity and individuality. We encourage you to…
Senior FPGA/ASIC Modem Engineer
Designs and implements FPGA-based modem chains for a LEO satellite system using SDR, focusing on high-throughput, secure communications and waveform flexibility.
FPGA Verification Engineer, Air Dominance and Strike for Fastwater Staffing
Designs and runs UVM-based verification environments for AMD/Xilinx FPGAs in flight-critical avionics, using SystemVerilog, UVM, and coverage-driven flows to meet DO-254 safety standards.