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FPGA Verification Engineer
FPGA Verification Engineer Level 3/4 - Linthicum Location: United States-Maryland-Linthicum Time Type: Full time Job Description RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR…
FPGA Verification Engineer
FPGA Verification Engineer Level 5 - Linthicum Location: United States-Maryland-Linthicum Time Type: Full time Job Description RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR START:…
Senior ASIC Design Engineer
Senior Engineer - ASIC Design Location: Bangalore,Karnataka,India Department: 76 Product Development Work Location: onsite Grow With Us: About this opportunity: We are starting a new Silicon R&D center in…
Lead Physical design Engineer
Lead the physical design and verification of processor subsystems IP, ensuring tapeout signoff for next-gen chips using EDA tools like Innovus and Fusion Compiler.
Design Verification Engineer
Design Verification Engineer at indie builds and executes verification strategies for next-gen automotive camera processors using SystemVerilog, UVM, and C/C++.
Physical Design Technical Lead, ASIC, TPU
Lead the physical design of next-generation AI silicon (TPUs) for Google, driving RTL-to-GDSII implementation, timing/power closure, and cross-functional collaboration to deliver high-performance custom chips.
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Designs and implements advanced ASIC/SOC chips for SpaceX’s Starlink network, focusing on physical design flows, timing closure, and signoff checks to enable global satellite internet connectivity.
Manager, ASIC Design Engineering (Starshield Silicon)
Lead a team designing ASICs and FPGAs for SpaceX’s Starshield satellite systems, overseeing RTL implementation, verification, and silicon bring-up to deliver high-speed data processing for national security missions.
Physical Design Engineer II (Silicon Engineering)
Designs and implements next-generation ASICs for SpaceX's Starlink network, focusing on physical design steps like synthesis, floorplanning, and place-and-route using industry-standard EDA tools.
Physical Design Engineer II (Silicon Engineering)
Designs and implements next-generation ASICs for SpaceX’s Starlink network, focusing on physical design steps like synthesis, floorplanning, and timing closure to enable global satellite internet connectivity.
Principal ASIC Design Engineer (Starshield)
Designs and verifies next-generation FPGAs and ASICs for SpaceX’s Starshield national security programs, using Verilog/SystemVerilog and collaborating with verification and physical implementation teams.
Sr. ASIC Design Engineer (Starshield)
Designs and verifies next-generation FPGAs and ASICs for SpaceX’s Starshield national security programs, using Verilog/SystemVerilog, EDA tools, and collaborating with verification and physical implementation teams.
Ingénieur DevOps F/H
CONTEXTE Vous rejoignez une équipe DevOps de 2 personnes au sein du pôle Search & Analytics de Coexya. Votre mission ? Accompagner les équipes projets réparties entre Lyon et Rennes dans l'industrialisation et…
Business Analyst MDM (F/H)
CONTEXTE Dans le cadre de nos activités, nous développons pour nos clients des solutions dédiées à la gestion de la donnée cliente : améliorer la qualité de la donnée client à travers sa fiabilisation, son…
Physical Design Leader
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…
Business Analyst Salesforce (F/H)
CONTEXTE Pour accompagner la croissance de notre entité spécialisée en CRM et Marketing digital, nous recherchons notre futur Business analyst Salesforce F/H. Acteur reconnu de la transformation numérique des…
DFT RTL Design Engineer
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…
Développeur Java F/H
CONTEXTE Coexya souhaite renforcer son entité de valorisation de données, et plus précisément son pôle spécialisé dans le domaine de la Santé, et recherche un Développeur JAVA F/H. Le pôle « Valorisation de données de…
IC RTL2GDS Architect, AE
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Overview The Architect will serve as a technical leader within Cadence’s North America Field Applications…
Design Automation Engineer
Design Automation Engineer develops and maintains static timing analysis (STA) flows and tools for advanced digital design projects using Synopsys PrimeTime and Cadence Tempus, with scripting in Python, Tcl, and Shell.