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Ingénieur principal en analogique/ Principal Engineer - Analog Design
Design, simulate, and validate high-speed analog and mixed-signal IP blocks (PLLs, ADCs, DACs, I/O interfaces) for SoC timing products using Cadence tools and Verilog-A.
Principal Engineer - Design
Principal Design Engineer at Microchip Technology leading hardware/firmware co-development and pre/post-silicon verification using emulators and FPGA platforms for SoC devices.
Senior Design Engineer - Security IP
Designs and verifies hardware security IP for SoCs, including cryptography, key management, and secure boot, using Verilog and scripting.
Sr. ASIC Design Engineer
Design and implement high-speed ASICs for networking routers and switches using Verilog/SystemVerilog, collaborating with physical design and verification teams to meet power, timing, and area targets.
Embedded Software Engineer
Design and implement embedded firmware for RF radar systems, integrating hardware/software components and developing user interfaces to validate radar algorithms.
Firmware Engineer
Design and implement FPGA firmware for next-gen radar and sensing systems, integrating with software and hardware for defense and commercial applications.
FPGA Engineer
Design and implement FPGA-based digital signal processing for next-gen radar and sensing systems, integrating with software and hardware in a defense-focused product company.
Sr. FPGA Engineer
Design and implement FPGA-based signal processing for next-gen radar and sensing systems, integrating with software and hardware in a defense-focused R&D environment.
FPGA Engineer
Designs and verifies FPGA-based digital circuits for automated trading systems, develops reusable IP, and integrates hardware with software stacks using SystemVerilog/Verilog/VHDL and C++.
RTL Design Technical Lead, Networking, Google Cloud
Leads RTL design for Google’s custom silicon solutions, focusing on ASIC development for SoC/VLSI, Verilog/SystemVerilog coding, and hardware-software integration to power Google Cloud and consumer products like Vertex AI.
Microprocessor VLSI Physical Design Engineer
Design high-speed VLSI circuits for next-gen CPUs, optimizing power, performance, and area while collaborating across teams to solve complex hardware challenges.
Ingénieur FPGA (H/F)
Design and implement embedded FPGA logic in VHDL/Verilog for safety-critical systems in aerospace, defense, and rail.
Senior Design Engineer, Networking, Google Cloud
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…
Silicon Design Engineer
Design and validate DSP and linear-algebra IP blocks for AMD FPGAs and AI Engine arrays using HDLs and C/C++.
ASIC/SoC Design Verification Engineer
Design and verify ASIC/SoC hardware using UVM, SystemVerilog, and Synopsys tools to catch silicon-critical bugs before tape-out.
Senior FPGA Team Lead
Lead a team to architect and implement FPGA-based signal processing systems for a space-based cellular broadband network, using VHDL/Verilog and Xilinx tools.
Lead Digital Design Engineer
Lead a team to architect and implement FPGA firmware in VHDL/Verilog for military-grade electro-optic systems, including video/image processing and high-speed data links.
해상용 레이다 스캐너 신호처리(FPGA) 엔지니어
Develop FPGA-based radar signal processing for marine navigation systems, implementing DSP algorithms like pulse compression and FFT in Verilog/VHDL.
Senior Principal Test Engineer
Design and develop automated test software and hardware for mission-critical electronic warfare systems, integrating NI Test Stand and RF measurement tools in a production environment.
Senior Test Engineer
Develops automated test software and hardware integration solutions for defense electronics, focusing on RF/microwave testing, troubleshooting, and production validation in a government/defense environment.