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Senior/Staff Front-End Engineer (SOC)
Design and implement Verilog RTL for SoC blocks, integrate IPs, and optimize performance through synthesis, timing closure, and power reduction in a semiconductor R&D team.
FPGA/Firmware Engineer
Designs and debugs FPGA firmware for X-ray detector systems, integrating hardware and optimizing high-speed interfaces like Gigabit Ethernet and PCIe.
ASIC Design and Integration Engineer – Silicon Security
Design and integrate secure ASIC subsystems to protect Apple’s SoCs from side-channel attacks and ensure data integrity using RTL, UPF, and cryptographic engines.
ASIC Design Verification Engineering Leader
Lead verification of Cisco’s cutting-edge data-center ASICs, building DV environments, writing test plans, and ensuring full coverage with Verilog/SystemVerilog/UVM while collaborating with designers and software teams.
Graduate Talent (Core Design Verification Engineer)
Designs and runs verification tests for Intel’s next-gen CPUs using SystemVerilog/UVM, debugging pre-silicon issues to ensure processor reliability and performance.
SOC Design Verification Engineer
Designs and runs SystemVerilog/UVM testbenches to verify Arm-based CPUs, PCIe, DDR, and SoC subsystems, writing C/C++/Assembly tests and debugging RTL issues.
Senior FPGA Engineer
Designs and verifies high-performance FPGA and SoC solutions in VHDL/Verilog, integrating IP and optimizing timing for mission-critical applications.
Senior RTL Design Engineer – PCIe Subsystems
Designs and implements PCIe subsystems for next-gen infrastructure SoCs using SystemVerilog/Verilog, collaborating with verification and implementation teams to ensure tape-out readiness.
Senior/ IC Design Engineer (Physical Design)
Designs and implements ASIC physical design flows (RTL-to-GDS) using EDA tools and AI-assisted methodologies to optimize PPA and timing for tape-out.
Principal FPGA Engineer II
Principal FPGA Engineer designing next-gen surgical camera tech using VHDL/Verilog, C/C++, and Python while leading a team and interfacing with hardware sensors and DDR memories.
Principal FPGA Image Pipeline Engineer
Lead FPGA design and image-processing pipelines for next-gen surgical cameras, writing VHDL/Verilog, C firmware, and test scripts while mentoring junior engineers.
Technical Staff Engineer - Design
Designs IO pad rings, bump patterns, and connectivity for advanced SoC storage/memory controllers using EDA tools and scripting.
Principal Engineer - Digital Design
Principal Digital Design Engineer designing secure embedded controllers and cryptographic hardware for automotive, industrial, and defense markets using ASIC/FPGA flows, Verilog/VHDL, and security countermeasures.
ASIC TOP Floorplan Design Engineer
We are now looking for an ASIC Top Floorplan Design Engineer. NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC's and GPU's. This position offers you a unique…
Lead FPGA /CPLD Engineer (Server & Storage-三重)
Lead a team designing CPLD/FPGA logic for server and storage products using Verilog/VHDL, I2C, SPI, and validation flows.
Principal Engineer - Analog Design
Designs and validates high-speed analog and mixed-signal IP blocks (PLLs, ADCs, DACs, filters) for multi-GHz timing products using Cadence tools and Verilog-A modeling.
Sr Engineer, Design
Designs and optimizes DFT strategies, test sequences, and firmware for NAND flash memory, using Verilog/XA simulations and collaborating with cross-functional teams.
Инженер-разработчик ПЛИС (FPGA designer)
Обязанности: Разработка и отладка проектов для ПЛИС. Документирование разработанных проектов. Требования: Высшее (техническое) образование, предпочтительно-в области радиотехники. Опыт работы от 3-х лет в разработке и…